SI3211PPTX-EVB Silicon Laboratories Inc, SI3211PPTX-EVB Datasheet - Page 125
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SI3211PPTX-EVB
Manufacturer Part Number
SI3211PPTX-EVB
Description
BOARD EVAL W/DISCRETE INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Specifications of SI3211PPTX-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3211
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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5. Pin Descriptions: Si3210/11
Pin #
QFN
35
36
37
38
1
2
3
4
TSSOP
SDCH/DIO1
SDCL/DIO2
Pin #
SRINGDC
1
2
3
4
5
6
7
8
STIPDC
FSYNC
RESET
QGND
CAPM
CAPP
V
IREF
DTX
DDA1
SDCH/DIO1
FSYNC
RESET
10
11
12 13
1
2
3
4
5
6
7
8
9
Name
PCLK
DRX
DTX
INT
CS
38
14
37
15 16 17 18 19
QFN
EPAD
36
35
Chip Select.
Active low. When inactive, SCLK and SDI are ignored and SDO is high
impedance. When active, the serial port is operational.
Interrupt.
Maskable interrupt output. Open drain output for wire-ORed operation.
PCM Bus Clock.
Clock input for PCM bus timing.
Receive PCM Data.
Input data from PCM bus.
Transmit PCM Data.
Output data to PCM bus.
Frame Synch.
8 kHz frame synchronization signal for the PCM bus. May be short or long
pulse format.
Reset.
Active low input. Hardware reset used to place all control registers in the
default state.
DC Monitor/General Purpose I/O.
DC-DC converter monitor input used to detect overcurrent situations in the
converter (Si3210 only). General purpose I/O (Si3211 only).
34 33 32
31
30
29
28
27
26
25
24
23
22
21
20
DCFF/DOUT
SDITHRU
DCDRV/DCSW
GNDD
ITIPN
ITIPP
IRINGP
IRINGN
IGMP
TEST
VDDD
V
DDA2
Rev. 1.5
SDCH/DIO1
SDCL/DIO2
SRINGDC
Description
SRINGE
STIPDC
FSYNC
RESET
SVBAT
QGND
CAPM
STIPE
CAPP
PCLK
V
IREF
DRX
DTX
DDA1
INT
CS
1
10
11
12
13
14
15
16
17
18
19
2
3
4
5
6
7
8
9
TSSOP
Si3210/Si3211
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
SCLK
SDO
SDITHRU
ITIPP
IRINGP
IRINGN
IGMP
IGMN
STIPAC
SDI
DCDRV/DCSW
DCFF/DOUT
TEST
GNDD
VDDD
ITIPN
V
GNDA
SRINGAC
DDA2
125
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