SI3211 ETC, SI3211 Datasheet
SI3211
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SI3211 Summary of contents
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C™ Features Performs all ...
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Si 3210/ Si3 211/S i32 12 2 Preliminary Rev. 1.11 ...
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... Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Interrupt Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 PCM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Indirect Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 DTMF Decoding (Si3210 and Si3211 only 108 Oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Digital Programmable Gain/Attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 SLIC Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 FSK Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Pin Descriptions: Si3210/11/ 115 Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Package Outline: 38-Pin TSSOP ...
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Si 3210/ Si3 211/S i32 12 Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information Parameter DC Supply Voltage Input Current, Digital Input Pins Digital Input Voltage ESD, Si3210/11/12 (Human Body Model) Operating Temperature Range Storage Temperature Range TSSOP-38 ...
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... Gain Variation with Temperature Gain Variation with Supply 2-Wire Return Loss Transhybrid Balance 4 Idle Channel Noise PSRR from VDDA PSRR from VDDD PSRR from VBAT Si3210/Si3211/Si3212 Test Condition TX/RX Performance THD = 1.5% 2-wire – PCM or PCM – 2-wire: 200 Hz–3.4 kHz 2 200 Hz to 3.4 kHz ...
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Si 3210/ Si3 211/S i32 12 Table 3. AC Characteristics (Continued 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Longitudinal to Metallic or PCM ...
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... Figure 1. Transmit and Receive Path SNDR Fundamental 5 Output Power (dBm0 2 Fundamental Input Power (dBm0) Figure 2. Overload Compression Performance Preliminary Rev. 1.11 Si3210/Si3211/Si3212 Acceptable Region ...
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Si 3210/ Si3 211/S i32 12 Figure 3. Transmit Path Frequency Response 8 Typical Response Typical Response Preliminary Rev. 1.11 ...
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... Si3210/Si3211/Si3212 Figure 4. Receive Path Frequency Response Preliminary Rev. 1.11 9 ...
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Si 3210/ Si3 211/S i32 12 Figure 5. Transmit Group Delay Distortion Figure 6. Receive Group Delay Distortion 10 Preliminary Rev. 1.11 ...
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... Trapezoidal Ring Crest Factor Accuracy Sinusoidal Ring Crest R Factor Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Power Alarm Threshold Accuracy DC resistance round trip; 160 *Note: Si3210/Si3211/Si3212 Test Condition See note mA, ETBA = 4 mA LIM Active Mode – V TIP ...
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Si 3210/ Si3 211/S i32 12 Table 5. Monitor ADC Characteristics ( 3. 70°C for K-Grade, –40 to 85°C for B-Grade) DDA DDD A Parameter Symbol Differential Nonlinearity DNLE (6-bit ...
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... Rise Time, RESET RESET Pulse Width Note: All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are V 0 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform. IL Si3210/Si3211/Si3212 Test Condition + I Sleep (RESET = 0) D Open ...
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Si 3210/ Si3 211/S i32 12 Table 10. Switching Characteristics—SPI 3. 70°C for K-Grade, –40 to 85°C for B-Grade, C DDA DDA A Parameter Cycle Time SCLK Rise Time, ...
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... All timing is referenced to the 50% level of the waveform. Input test levels are V 2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0). PCLK FSYNC DRX t DTX Figure 8. PCM Highway Interface Timing Diagram Si3210/Si3211/Si3212 = Test Symbol Conditions 1 dty ...
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Si 3210/ Si3 211/S i32 12 Q1 5401 R10 10 TIP Q6 5551 C8 C5 220nF 22nF Protection Circuit R6 C6 80.6 22nF RING Notes: 1. Values and configurations for these components can be derived from Table 19 or from ...
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... Ultra Fast Recovery 200 V, 1A Rectifier L1 1A, Shielded Inductor (See AN45 Table 19 for value selection) Q7 120 V, High Current Switching PNP General Purpose Switching NPN *Note: Voltage rating of this device must be greater than V Si3210/Si3211/Si3212 VDC F1 1 R19 C25 2 Note 1 1 R18 ...
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Si 3210/ Si3 211/S i32 12 Figure 11. Si3210M MOSFET/Transformer DC-DC Converter Circuit Table 14. Si3210M MOSFET/Transformer DC-DC Converter Component Values Component ( 100 V, Electrolytic, ±20% C14* C25* C27 470 pF, 100 V, X7R, ±20% R17 ...
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... RING Notes: 1. Only one component per system needed. 2. All circuit grounds should have a single-point connection to the ground plane. VBATL Figure 12. Si3211/12 Typical Application Circuit Using Extended Battery Table 15. Si3211/12 External Component Values Component C1, Ceramic/Tantalum Low Leakage Electrolytic, 20% ...
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Si 3210/ Si3 211/S i32 12 RRE Figure 13. Si321x Optional Equivalent Q5, Q6 Bias Circuit Table 16. Si321x Optional Bias Component Values Component C7,C8 100 nF, 100 V, X7R, 20% R23,R24 3 1/ The subcircuit ...
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... Figure 14. Open circuit TIP-to-RING voltage (V ) defines the constant OC voltage zone and is programmable from 94 Si3210/Si3211/Si3212 1.5 V steps. The loop current limit (I constant current zone and is programmable from steps. The ProSLIC has an inherent dc output resistance (R ...
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Si 3210/ Si3 211/S i32 12 Linefeed Architecture The ProSLIC is a low-voltage CMOS device that uses low-cost external components to control the high voltages required for subscriber Figure simplified illustration of the linefeed control loop circuit ...
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... Forward Active 010 Forward On-Hook Transmission 011 TIP Open 100 Ringing 101 Reverse Active 110 Reverse On-Hook Transmission 111 Ring Open Note: The Linefeed register (LF) is located in direct Register 64. Si3210/Si3211/Si3212 M onitor A/D A/D DSP D/A SLIC DAC DC Sense Control Loop R BP ...
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Si 3210/ Si3 211/S i32 12 Table 22. Measured Realtime Linefeed Interface Characteristics Parameter Loop Voltage Sense (V – V TIP RING Loop Current Sense TIP Voltage Sense RING Voltage Sense Battery Voltage Sense BAT Battery Voltage ...
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... Automatic/Manual Detect *Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). Si3210/Si3211/Si3212 Description/ Resolution Range points to Q1 ...
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Si 3210/ Si3 211/S i32 12 LCS Input ISP_OUT Signal LVS Processor LFS LCVE Loop Closure Detection A loop closure event signals that the terminal equipment has gone off-hook during on-hook transmission or on- hook active states. The ProSLIC performs ...
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... For higher channel count applications where centralized battery voltage supply is economical, or for modular legacy systems where battery voltage is already available, the Si3211 and Si3212 are recommended. DC-DC Converter General Description (Si3210/Si3210M Only) ...
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Si 3210/ Si3 211/S i32 12 and average input currents can become large with small input voltages. Consider this when selecting the appropriate input voltage and power rating for the V power supply (number of REN supported). For this solution, ...
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... Low Battery Voltage—V BATL V OV Note: The ProSLIC uses registers that are both directly and indirectly mapped. A “direct” register is one that is mapped directly. An “indirect” register is one that is accessed using the indirect access registers (direct registers 28 through 31). Si3210/Si3211/Si3212 LIM V ...
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... External Battery Switching (Si3211 and Si3212 Only) The Si3211 and Si3212 support switching between two battery voltages. The circuit for external battery switching is defined in Figure 12. Typically a high voltage battery (e.g., – used for on-hook and ringing states, and a low voltage battery (e.g., – ...
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... OSC1 0.78434 2 25701 = = 1 0.21556 OSC1X = -------------------- - 2 – 1.78434 OSC1Y = 0 Si3210/Si3211/Si3212 8 kHz OZn Clock Zero Cross O SSn Enable Two-Pole Resonance Oscillator R egister Load Load Logic O SCn OnIP REL* INT Logic O SCnX O nIE O nAP INT Logic O SCnY O nAE ...
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Si 3210/ Si3 211/S i32 12 time the 16-bit counter will reset to zero and begin counting until the inactive timer expires. The cadence continues until the user clears the O1TAE and O1TIE control bits. The zero crossing detect feature ...
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... Ringing Generation The ProSLIC provides fully programmable internal balanced ringing with or without a dc offset to ring a wide variety of terminal devices. All parameters associated with ringing are software programmable: ringing frequency, waveform, amplitude, dc offset, and Si3210/Si3211/Si3212 ... ... ... 0 IT1 0,1 ringing cadence. Both sinusoidal and trapezoidal ringing waveforms are supported, and the trapezoidal crest factor is programmable ...
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Si 3210/ Si3 211/S i32 12 Table 28. Registers for Ringing Generation Parameter Ringing Waveform Ringing Voltage Offset Enable Ringing Active Timer Enable Ringing Inactive Timer Enable Ringing Oscillator Enable Ringing Oscillator Active Timer Ringing Oscillator Inactive Timer Linefeed Control ...
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... RNGY Si3210/Si3211/Si3212 RNGX 71 V For a crest factor of 1.3 and a period of 0.05 sec (20 Hz), the rise time requirement is 0.0153 sec. ringing. Figure 20 RCO 1.3 crest factor In addition, the user must select the trapezoidal ringing waveform by writing TSWS = 1 in direct Register 34. ...
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... Si 3210/ Si3 211/S i32 12 leakages, etc. The total I LOAD,PK smaller than 80 mA ------------ - 80 OVR LOAD,PK where is the minimum expected current gain of transistors Q5 and Q6. The minimum value for VBATH is therefore given by the following: VBATH AC,PK ROFF The ProSLIC is designed to create a fully balanced ...
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... Generation" on page 30 with the exception that the sample rate for computation is 64 kHz instead of 8 kHz. The equations are as follows ------------------------- - coeff = cos 64000 Hz 15 PLSCO coeff 2 = Si3210/Si3211/Si3212 Register RTIP RTIE RTDI[6:0] RPTP[5:0] NRTP[12:0] RTP RPTP hex decimal 0200 34 mA 3600 0320 34 mA ...
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Si 3210/ Si3 211/S i32 12 Table 31. Associated Pulse Metering Generator Registers Parameter Pulse Metering Frequency Coefficient Pulse Metering Amplitude Coefficient Pulse Metering Attack/Decay Ramp Rate Pulse Metering Active Timer Pulse Metering Inactive Timer Pulse Metering Control Status and ...
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... Depending on the PCM_Mode register selection, every 8-bit compressed serial data word will occupy one time slot on the PCM highway, uncompressed serial data word will occupy two time slots on the PCM highway. Si3210/Si3211/Si3212 or every 16-bit Preliminary Rev. 1.11 39 ...
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Off Chip On Chip HYBP From Billing Tone H DAC + – H HYBA TIP RING – + XAC I G RAC buf m From Billing Tone DAC Figure 23. AC Signal Path Block Diagram Transmit Path ATX Decimation A/D ...
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... From this point of view, at frequencies greater than 4 kHz, the plot in Figure 4 Si3210/Si3211/Si3212 should be interpreted as the maximum allowable magnitude of any spurious signals that are generated when a PCM data stream representing a sine wave signal in the range of 300 ...
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... Interrupt Logic The ProSLIC is capable of generating interrupts for the following events: Loop current/ring ground detected Ring trip detected Power alarm DTMF digit detected (Si3210 and Si3211 only) (XAC) and a Active timer 1 expired Inactive timer 1 expired Active timer 2 expired ...
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... The clock should return to a logic high when no transfer is in progress. Si3210/Si3211/Si3212 Indirect registers are accessed through direct registers 29 through 30. Instructions on how to access them is described in “Control Registers” beginning on page 50. ...
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Si 3210/ Si3 211/S i32 12 SCLK CS SDI SDO SCLK CS SDI SDO High Impedance 44 Don't Care High Impedance Figure 24. Serial Write 8-Bit Mode Don't ...
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... SDI2 – – SDI3 – – – ote: During chip select byte, SD ITHR delayed by one SC LK. Each device daisy-chained looks at the LSB of the chip select byte for its chip select. Si3210/Si3211/Si3212 CS SDO CS SDO C S SDO ...
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Si 3210/ Si3 211/S i32 12 PCM Interface The ProSLIC contains a flexible programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled via the PCLK and FSYNC inputs as well as the PCM ...
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... Law is more commonly used in North America and Japan, while A-Law is primarily used in Europe. Data format is selected via the PCMF register. Tables 32 and 33 define the -Law and A-Law encoding formats. Si3210/Si3211/Si3212 2 3 ...
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Si 3210/ Si3 211/S i32 12 Table 32. -Law Encode-Decode Characteristics Segment #Intervals X Interval Size Number 256 128 ...
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... Notes: 1. Characteristics are symmetrical about analog zero with sign bit = 0 for negative values. 2. Digital code includes inversion of all even numbered bits. Si3210/Si3211/Si3212 Value at segment endpoints Digital Code 4096 3968 10101010b . . 2176 2048 10100101b ...
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... Interrupt Status 2 20 Interrupt Status 3 21 Interrupt Enable 1 22 Interrupt Enable 2 23 Interrupt Enable 3 24 Decode Status Notes: 1. Si3211 and Si3212 only. 2. Si3210 only. 3. Si3210 and Si3211 only. 50 Table 34. Direct Register Summary Bit 7 Bit 6 Bit 5 Bit 4 Setup SPIDC SPIM PNI[1:0] PCME PCMF[1:0] TXS[7:0] ...
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... Oscillator Active Timer— Low Byte 45 Pulse Metering Oscillator Active Timer— High Byte 46 Pulse Metering Oscillator Inactive Timer—Low Byte Notes: 1. Si3211 and Si3212 only. 2. Si3210 only. 3. Si3210 and Si3211 only. Si3210/Si3211/Si3212 Bit 7 Bit 6 Bit 5 Bit 4 IDA[7:0] IDA[15:8] Oscillators OSS1 ...
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... Common Mode Voltage 74 High Battery Voltage 75 Low Battery Voltage 76 Power Monitor Pointer 77 Line Power Output Monitor 78 Loop Voltage Sense Notes: 1. Si3211 and Si3212 only. 2. Si3210 only. 3. Si3210 and Si3211 only. 52 Bit 7 Bit 6 Bit 5 Bit 4 PIT[15:8] RAT[7:0] RAT[15:8] RIT[7:0] RIT[15:8] SLIC LCD[7:0] LFS[2:0] SQH ...
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... TIP Gain Mismatch Calibration Result 100 Differential Loop Current Gain Calibration Result 101 Common Mode Loop Current Gain Calibration Result Notes: 1. Si3211 and Si3212 only. 2. Si3210 only. 3. Si3210 and Si3211 only. Si3210/Si3211/Si3212 Bit 7 Bit 6 Bit 5 Bit 4 LCSP VTIP[7:0] VRING[7:0] VBATS1[7:0] VBATS2[7:0] ...
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... DAC Offset Calibration Result 106 Common Mode Balance Calibration Result 107 DC Peak Voltage Calibration Result 108 Enhancement Enable Notes: 1. Si3211 and Si3212 only. 2. Si3210 only. 3. Si3210 and Si3211 only. 54 Bit 7 Bit 6 Bit 5 Bit 4 CALMG1[3:0] DACOF[7:0] 2 ILIMEN FSKEN DCEN ZSEXT Preliminary Rev. 1.11 Bit 3 ...
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... Enable SPI daisy chain mode. 6 SPIM SPI Mode Causes SDO to tri-state on rising edge of SCLK of LSB Normal operation; SDO tri-states on rising edge of CS. 5:4 PNI[1:0] Part Number Identification Si3210 01 = Si3211 10 = Si3212 11 = Si3210M 3:0 RNI[3:0] Revision Number Identification. 0001 = Revision A, 0010 = Revision B, 0011 = Revision C, etc. Si3210/Si3211/Si3212 D5 D4 ...
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Si 3210/ Si3 211/S i32 12 Register 1. PCM Mode Select Bit D7 D6 Name PCME Type Reset settings = 0000_1000 Bit Name 7:6 Reserved Read returns zero. 5 PCME PCM Enable Disable PCM transfers Enable ...
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... Name Type Reset settings = 0000_0000 Bit Name 7:2 Reserved Read returns zero. 1:0 RXS[9:8] PCM Receive Start Count. PCM receive start count equals the number of PCLKs following FSYNC before data reception begins. See Figure 27 on page 46. Si3210/Si3211/Si3212 Function RXS[7:0] R/W Function D5 D4 ...
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... Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 DOUT DOUT Pin Output Data (Si3211/Si3212 only DOUT pin driven low DOUT pin driven high. Si3210 = Reserved. 3 DIO2 DIO2 Pin Input/Output Direction DIO2 pin is an input DIO2 pin is an output and driven to value of the PD2 bit. ...
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... Full analog loopback mode enabled. 1 DLM Digital Loopback Mode. (See Figure 23 on page 40 Digital loopback disabled Digital loopback enabled. 0 ALM1 Analog Loopback Mode 1. (See Figure 23 on page 40 Analog loopback disabled Analog loopback enabled. Si3210/Si3211/Si3212 ALM2 R/W Function Preliminary Rev. 1. ...
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Si 3210/ Si3 211/S i32 12 Register 9. Audio Gain Control Bit D7 D6 Name RXHP TXHP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 RXHP Receive Path High Pass Filter Disable HPF enabled in receive ...
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... Two-wire impedance synthesis enabled. 2:0 TISS[2:0] Two-Wire Impedance Synthesis Selection. 000 = 600 001 = 900 010 = 600 011 = 900 100 = CTR21 (270 101 = Australia/New Zealand #1 (220 110 = Slovakia/Slovenia/South Africa (220 111 = New Zealand #2 (370 Si3210/Si3211/Si3212 CLC[1:0] TISE R/W R/W Function + 2. 2. 750 || 150 nF) ...
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Si 3210/ Si3 211/S i32 12 Register 11. Hybrid Control Bit D7 D6 Name HYBP[2:0] Type Reset settings = 0011_0011 Bit Name 7 Reserved Read returns zero. 6:4 HYBP[2:0] Pulse Metering Hybrid Adjustment. 000 = 4.08 dB 001 = 2.5 ...
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... Override automatic control and force pulse metering DAC circuitry on. 4 DCOF DC-DC Converter Power-Off Control (Si3210 only Automatic power control Override automatic control and force dc-dc circuitry off. Si3211/Si3212 = Read returns 1; it cannot be written. 3 MOF Monitor ADC Power-Off Control Automatic power control Override automatic control and force monitor ADC circuitry off. ...
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Si 3210/ Si3 211/S i32 12 Register 15. Power Down Control 2 Bit D7 D6 Name ADCM Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 ADCM Analog to Digital Converter Manual/Automatic Power Control ...
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... Oscillator 1 Inactive Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 O1AP Oscillator 1 Active Timer Interrupt Pending. Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. Si3210/Si3211/Si3212 RGAP O2IP O2AP R/W R/W R/W Function Preliminary Rev ...
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Si 3210/ Si3 211/S i32 12 Register 19. Interrupt Status 2 Bit D7 D6 Name Q6AP Q5AP Q4AP Type R/W R/W Reset settings = 0000_0000 Bit Name 7 Q6AP Power Alarm Q6 Interrupt Pending. Writing 1 to this bit clears ...
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... This bit is set once a pending indirect register service request has been completed. Writ- ing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. 0 DTMFP DTMF Tone Detected Interrupt (Si3210 and Si3211 only). Writing 1 to this bit clears a pending interrupt interrupt pending Interrupt pending. Si3212 = Reserved; read returns 0. Si3210/Si3211/Si3212 ...
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Si 3210/ Si3 211/S i32 12 Register 21. Interrupt Enable 1 Bit D7 D6 Name PMIE PMAE RGIE Type R/W R/W Reset settings = 0000_0000 Bit Name 7 PMIE Pulse Metering Inactive Timer Interrupt Enable Interrupt masked. 1 ...
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... Interrupt enabled. 2 Q1AE Power Alarm Q1 Interrupt Enable Interrupt masked Interrupt enabled. 1 LCIE Loop Closure Transition Interrupt Enable Interrupt masked Interrupt enabled. 0 RTIE Ring Trip Interrupt Enable Interrupt masked Interrupt enabled. Si3210/Si3211/Si3212 Q3AE Q2AE Q1AE R/W R/W R/W Function Preliminary Rev. 1. LCIE RTIE ...
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... CMCE Common Mode Calibration Error Interrupt Enable Interrupt masked Interrupt enabled. 1 INDE Indirect Register Access Serviced Interrupt Enable Interrupt masked Interrupt enabled. 0 DTMFE DTMF Tone Detected Interrupt Enable (Si3210 and Si3211 only Interrupt masked Interrupt enabled. Si3212 = Reserved. 70 Si3210/Si3211 CMCE R/W ...
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... VAL DTMF Valid Digit Decoded Not currently detecting digit Currently detecting digit. Si3212 = Reserved; read returns 0. 3:0 DIG[3:0] DTMF Digit (Si3210 and Si3211 only). 0001 = “1” 0010 = “2” 0011 = “3” 0100 = “4” 0101 = “5” 0110 = “6” ...
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Si 3210/ Si3 211/S i32 12 Register 28. Indirect Data Access—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 IDA[7:0] Indirect Data Access—Low Byte. A write to IDA followed by a write to IAA will ...
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... Register 31. Indirect Address Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 IAS Indirect Access Status indirect memory access pending Indirect memory access pending. Si3210/Si3211/Si3212 IAA[7:0] R/W Function Function Preliminary Rev. 1. ...
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Si 3210/ Si3 211/S i32 12 Register 32. Oscillator 1 Control Bit D7 D6 Name OSS1 REL Type R R/W Reset settings = 0000_0000 Bit Name 7 OSS1 Oscillator 1 Signal Status Output signal inactive Output ...
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... Oscillator 2 Inactive Timer Enable Disable timer Enable timer. 2 O2E Oscillator 2 Enable Disable oscillator Enable oscillator. 1:0 O2SO[1:0] Oscillator 2 Signal Output Routing Unassigned path (output not connected Assign to transmit path Assign to receive path Assign to both paths. Si3210/Si3211/Si3212 OZ2 O2TAE O2TIE R/W R/W R/W Function Preliminary Rev. 1. ...
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Si 3210/ Si3 211/S i32 12 Register 34. Ringing Oscillator Control Bit D7 D6 Name RSS RDAC Type R Reset settings = 0000_0000 Bit Name 7 RSS Ringing Signal Status Ringing oscillator output signal inactive Ringing ...
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... Pulse Metering Active Timer Enable Disable timer Enable timer. 3 PMIE Pulse Metering Inactive Timer Enable Disable timer Enable timer. 2 PMOE Pulse Metering Oscillator Enable Disable oscillator Enable oscillator. 1:0 Reserved Read returns zero. Si3210/Si3211/Si3212 PMAE PMIE PMOE R/W R/W R/W Function Preliminary Rev. 1. ...
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Si 3210/ Si3 211/S i32 12 Register 36. Oscillator 1 Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT1[7:0] Oscillator 1 Active Timer. LSB = 125 s Register 37. Oscillator 1 Active Timer—High ...
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... Reset settings = 0000_0000 Bit Name 7:0 OAT2[7:0] Oscillator 2 Active Timer. LSB = 125 s Register 41. Oscillator 2 Active Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OAT2[15:8] Oscillator 2 Active Timer. Si3210/Si3211/Si3212 OIT1[15:8] R/W Function OAT2[7:0] R/W Function OAT2[15:8] R/W Function Preliminary Rev. 1.11 ...
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Si 3210/ Si3 211/S i32 12 Register 42. Oscillator 2 Inactive Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 OIT2[7:0] Oscillator 2 Inactive Timer. LSB = 125 s Register 43. Oscillator 2 Inactive Timer—High ...
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... Bit Name 7:0 PIT[7:0] Pulse Metering Inactive Timer. LSB = 125 s Register 47. Pulse Metering Oscillator Inactive Timer—High Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 PIT[15:8] Pulse Metering Inactive Timer. Si3210/Si3211/Si3212 PAT[15:8] R/W Function PIT[7:0] R/W Function PIT[15:8] R/W Function Preliminary Rev ...
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Si 3210/ Si3 211/S i32 12 Register 48. Ringing Oscillator Active Timer—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 RAT[7:0] Ringing Active Timer. LSB = 125 s Register 49. Ringing Oscillator Active Timer—High Byte ...
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... LCD[7:0] Loop Closure Debounce Interval for Automatic Ringing. This register sets the loop closure debounce interval for the ringing silent period when using automatic ringing cadences. The value may be set between 0 ms (0x00) and 159 ms (0x7F) in 1.25 ms steps. Si3210/Si3211/Si3212 RIT[15:8] ...
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Si 3210/ Si3 211/S i32 12 Register 64. Linefeed Control Bit D7 D6 Name LFS[2:0] Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6:4 LFS[2:0] Linefeed Shadow. This register reflects the actual realtime linefeed state. Automatic ...
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... Reserved 1:0 ETBA[1:0] External Transistor Bias Levels—Active Off-Hook State. DC bias current which flows through external BJTs in the active off-hook state. Increasing this value increases the compliance of the ac longitudinal balance circuit Reserved Si3210/Si3211/Si3212 CBY ETBE ETBO[1:0] R/W R/W R/W Function Preliminary Rev ...
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... FVBAT V Manual Setting (Si3210 only). BAT 0 = Normal operation tracks VBATH register. BAT Si3211/Si3212 = Read returns 0; it cannot be written. 2 Reserved Si3210 = Read returns zero. Si3211/Si3212 = Read returns one. 1 BATSL Battery Feed Select (Si3211/Si3212 only). This bit selects between high and low battery supplies. ...
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... Enter off-hook active state automatically upon ring trip detect. 1 AOLD Automatic/Manual Loop Closure Detect Manual mode Enter off-hook active state automatically upon loop closure detect. 0 AOPN Power Alarm Automatic/Manual Detect Manual mode Enter open state automatically upon power alarm. Si3210/Si3211/Si3212 SPDS ABAT AORD R/W R/W R/W Function Preliminary Rev ...
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Si 3210/ Si3 211/S i32 12 Register 68. Loop Closure/Ring Trip Detect Status Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2 DBIRAW Ring Trip/Loop Closure Unfiltered Output. State of this bit ...
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... Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 ILIM[2:0] Loop Current Limit. The value written to this register sets the constant loop current. The value may be set between 20 mA (0x00) and 41 mA (0x07 steps. Si3210/Si3211/Si3212 RTDI[6:0] R/W Function Function Preliminary Rev ...
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Si 3210/ Si3 211/S i32 12 Register 72. On-Hook Line Voltage Bit D7 D6 Name VSGN Type R/W Reset settings = 0010_0000 Bit Name 7 Reserved Read returns zero. 6 VSGN On-Hook Line Voltage. The value written to this bit ...
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... The value written to this register sets high battery voltage. VBATH must be greater than or equal to VBATL. The value may be set between 0 V (0x00) and –94.5 V (0x3F) in 1.5 V steps. Default value = –75 V. For Si3211 and Si3212, VBATH must be set equal to externally supplied V Register 75. Low Battery Voltage ...
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Si 3210/ Si3 211/S i32 12 Register 76. Power Monitor Pointer Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:3 Reserved Read returns zero. 2:0 PWRMP[2:0] Power Monitor Pointer. Selects the external transistor from which to read ...
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... This register reports the polarity of the loop current Positive loop current (forward direction Negative loop current (reverse direction). 5:0 LCS[5:0] Loop Current Sense Magnitude. This register reports the magnitude of the loop current. The range 1.27 mA steps. Si3210/Si3211/Si3212 LVS[5:0] R Function > ...
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Si 3210/ Si3 211/S i32 12 Register 80. TIP Voltage Sense Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 VTIP[7:0] TIP Voltage Sense. This register reports the realtime voltage at TIP with respect to ground. The ...
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... Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ2[7:0] Transistor 2 Current Sense. This register reports the realtime current through Q2. The range (0x00) to 81.35 mA (0xFF) in .319 mA steps. If ETBE = 1, the reported value does not include the additional ETBO/A current. Si3210/Si3211/Si3212 VBATS2[7:0] R Function ...
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Si 3210/ Si3 211/S i32 12 Register 86. Transistor 3 Current Sense Bit D7 D6 Name Type Reset settings = xxxx_xxxx Bit Name 7:0 IQ3[7:0] Transistor 3 Current Sense. This register reports the realtime current through Q3. The range is ...
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... DC-DC Converter Period. This bit sets the PWM period for the dc-dc converter. The range is 3.906 s (0x40) to 15.564 s (0xFF) in 61.035 ns steps. Si3211/Si3212 = Reserved. Bit 6 is fixed to one and read-only, so there are two ranges of operation: 3.906 s–7.751 s, used for MOSFET transistor switching. 11.719 s–15.564 s, used for BJT transistor switching. ...
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... DCFF pin polarity is opposite of DCDRV pin (Si3210 DCFF pin polarity is same as DCDRV pin (Si3210M). Si3211/Si3212 = Reserved. 4:0 DCTOF[4:0] DC-DC Converter Minimum Off Time (Si3210 only). This register sets the minimum off time for the pulse width modulated dc-dc converter control. T Si3211/Si3212 = Reserved. 98 Si3210 DCTOF[4:0] R ...
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... Name Type Reset settings = 0000_0000 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 DCPW[7:0] DC-DC Converter Pulse Width (Si3210 only). Pulse width of DCDRV is given (DCPW – DCTOF – 4) 61.035 ns. Si3211/Si3212 = Reserved. Si3210/Si3211/Si3212 Si3210 DCPW[7:0] R Si3211/Si3212 Function Preliminary Rev. 1.11 D2 ...
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Si 3210/ Si3 211/S i32 12 Register 96. Calibration Control/Status Register 1 Bit D7 D6 Name CAL CALSP Type R/W Reset settings = 0001_1111 Bit Name 7 Reserved Read returns zero. 6 CAL Calibration Control/Status Bit. Setting this bit begins ...
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... Setting this bit begins calibration of the audio ADC offset Normal operation or calibration complete Calibration enabled or in progress. 0 CALCM Common Mode Balance Calibration. Setting this bit begins calibration of the ac longitudinal balance Normal operation or calibration complete Calibration enabled or in progress. Si3210/Si3211/Si3212 CALM1 CALM2 CALDAC R/W R/W ...
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Si 3210/ Si3 211/S i32 12 Register 98. RING Gain Mismatch Calibration Result Bit D7 D6 Name Type Reset settings = 0001_0000 Bit Name 7:5 Reserved Read returns zero. 4:0 CALGMR[4:0] Gain Mismatch of IE Tracking Loop for RING Current. ...
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... Current Limit Calibration Result. Register 103. Monitor ADC Offset Calibration Result Bit D7 D6 Name CALMG1[3:0] Type R/W Reset settings = 1000_1000 Bit Name 7:4 CALMG1[3:0] Monitor ADC Offset Calibration Result 1. 3:0 CALMG2[3:0] Monitor ADC Offset Calibration Result 2. Si3210/Si3211/Si3212 CALGC[4:0] R/W Function Function Function Preliminary Rev. 1. ...
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Si 3210/ Si3 211/S i32 12 Register 104. Analog DAC/ADC Offset Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:4 Reserved Read returns zero. 3 DACP Positive Analog DAC Offset. 2 DACN Negative Analog DAC Offset. 1 ...
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... Register 107. DC Peak Current Monitor Calibration Result Bit D7 D6 Name Type Reset settings = 0000_1000 Bit Name 7:4 Reserved Read returns zero. 3:0 CMDCPK[3:0] DC Peak Current Monitor Calibration Result. Si3210/Si3211/Si3212 Function Preliminary Rev. 1. CMDCPK[3:0] R/W 105 ...
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... When enabled, this bit invokes a multi-threshold error control algorithm which allows the dc-dc converter to adjust more quickly to voltage changes Normal control algorithm used Multi-threshold error control algorithm used. 106 Si3210 ZSEXT LCVE R/W R/W Si3211/Si3212 ZSEXT SWDB LCVE R/W R/W Function Preliminary Rev. 1. ...
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... Internal resistor used to generate 600 + 2.1 F and 900 + 2.16 F impedances Internal resistor removed from circuit. 3 SWDB Battery Switch Debounce (Si3211 and Si3212 only). When enabled, this bit allows debouncing of the battery switching circuit only when tran- sitioning from debounce used debounce period used. ...
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... For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an interrupt, IND (Register 20), can be generated upon completion of the indirect transfer. DTMF Decoding (Si3210 and Si3211 only) All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the reset state. ...
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... DTMF Power Minimum Threshold. This register sets the threshold for the minimum total power in the DTMF calculation, under which the calculation is ignored. 12 DTMF Hot Limit Threshold. This register sets the two-step AGC in the DTMF path. Si3210/Si3211/Si3212 Description Preliminary Rev. 1.11 Reference Page 38 ...
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Si 3210/ Si3 211/S i32 12 Oscillators See functional description sections of tone generation, ringing, and pulse metering for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined ...
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... Transmit Path Analog to Digital Converter Gain/Attenuation. This register sets gain/attenuation for the transmit path. The digitized signal is effectively multiplied by ADCG to achieve gain/attenuation. A value of 0x00 corresponds to – dB gain (mute). A value of 0x400 corresponds to unity gain. A value of 0x7FF corresponds to a gain of 6 dB. Si3210/Si3211/Si3212 Description D11 D10 D9 ...
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Si 3210/ Si3 211/S i32 12 SLIC Control See descriptions of linefeed interface and power monitoring for guidelines on computing register values. All values are represented in twos-complement format. Note: The values of all indirect registers are undefined following the ...
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... REL = 1 (direct Register 32, bit 6). Table 43. FSK Control Indirect Registers Summary Addr. D15 D14 D13 D12 99 100 101 102 103 104 Si3210/Si3211/Si3212 Description , to be supplied by the dc-dc converter. OV should be set between 0 and should be set between 0 and 13 D11 D10 D9 D8 ...
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Si 3210/ Si3 211/S i32 12 Table 44. FSK Control Indirect Registers Description Addr. 99 FSK Amplitude Coefficient for Space. When FSKEN = 1 and REL = 1, this register sets the amplitude to be used when gener- ating a ...
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... Active low input. Hardware reset used to place all control registers in the default state. 8 SDCH/DIO1 DC Monitor/General Purpose I/O. DC-DC converter monitor input used to detect overcurrent situations in the converter (Si3210 only). General purpose I/O (Si3211/Si3212 only). 9 SDCL/DIO2 DC Monitor/General Purpose I/O. DC-DC converter monitor input used to detect overcurrent situations in the converter (Si3210 only) ...
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Si 3210/ Si3 211/S i32 12 Pin # Pin Name 10 VDDA1 Analog Supply Voltage. Analog power supply for internal analog circuitry. 11 IREF Current Reference. Connects to an external resistor used to provide a high accuracy reference current. 12 ...
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... DCFF/DOUT DC Feed-Forward/High Current General Purpose Output. Feed-forward drive of external bipolar transistors to improve dc-dc converter efficiency (Si3210 only). High current output pin (Si3211/Si3212 only). 34 DCDRV/DCSW DC Drive/Battery Switch. DC-DC converter control signal output which drives external bipolar transistor (Si3210 only). Battery switch control signal output which drives external bipolar transistor (Si3211/Si3212 only) ...
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... Si 3210/ Si3 211/S i32 12 Ordering Guide Chip Description Si3210-KT ProSLIC Si3210-BT ProSLIC Si3210M-KT ProSLIC Si3210M-BT ProSLIC Si3211-KT ProSLIC Si3211-BT ProSLIC Si3212-KT ProSLIC Si3212-BT ProSLIC 118 Table 45. Ordering Guide DC-DC DTMF DCFF Pin Converter Decoder Output = DCDRV = DCDRV = DCDRV = DCDRV n/a n/a n/a n/a Preliminary Rev. 1.11 Package ...
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... Figure 31 illustrates the package details for the Si321x. Table 46 lists the values for the dimensions shown in the illustration. D Figure 31. 38-pin Thin Shrink Small Outline Package (TSSOP) Table 46. Package Diagram Dimensions Symbol Si3210/Si3211/Si3212 Inches Millimeters Min Max Min — 0.047 — ...
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... MOSFET/Transformer DC-DC Converter: Added Table 13: Si3210M External Component Values— BMOSFET/Transformer: Added Figure 11: Si3211/12 Typical Application Circuit Using External Battery: Updated Table 14: Si3211/12 External Component Values— External Battery: Updated Figure 12: Si321x Optional Equivalent Q5, Q6 Bias Circuit: Added Table 15: Si321x Optional Bias Component Values: ...
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... Si3210/Si3211/Si3212 Preliminary Rev. 1.11 121 ...
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Si 3210/ Si3 211/S i32 12 Contact Information Silicon Laboratories Inc. 4635 Boston Lane Austin, TX 78735 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: productinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be ...