SI3211 ETC, SI3211 Datasheet - Page 108

• Manufacturer Part Number: SI3211
• Description: PROSLIC PROGRAMMABLE CMOS SLIC/CODEC WITH RINGING/BATTERY VOLTAGE GENERATION
• Manufacturer: ETC

Si 3210/ Si3 211/S i32 12
Indirect Registers
Indirect registers are not directly mapped into memory but are accessible through the IDA and IAA registers. A
write to IDA followed by a write to IAA is interpreted as a write request to an indirect register. In this case, the
contents of IDA are written to indirect memory at the location referenced by IAA at the next indirect register update.
A write to IAA without first writing to IDA is interpreted as a read request from an indirect register. In this case, the
value located at IAA is written to IDA at the next indirect register update. Indirect registers are updated at a rate of
16 kHz. For pending indirect register transfers, IAS (direct Register 31) will be one until serviced. In addition an
interrupt, IND (Register 20), can be generated upon completion of the indirect transfer.
DTMF Decoding (Si3210 and Si3211 only)
All values are represented in twos-complement format.
Note: The values of all indirect registers are undefined following the reset state.
108
Addr.
Addr. D15
10
12
11
0
1
0
1
2
3
4
5
6
7
8
9
DTMF Row 0 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 0 DTMF detection. If the ratio of
power in row 0 to total power in the row band is greater than ROW0, then a row 0 signal is
detected. A value of 0x7FF0 corresponds to a 1.0 ratio.
DTMF Row 1 Peak Magnitude Pass Ratio Threshold.
This register sets the minimum power ratio threshold for row 1 DTMF detection. If the ratio of
power in row 1 to total power in the row band is greater than ROW1, then a row 1 signal is
detected. A value of 0x7FF0 corresponds to a 1.0 ratio.
D14
D13
D12
Table 36. DTMF Indirect Registers Description
Table 35. DTMF Indirect Registers Summary
D11
D10
Preliminary Rev. 1.11
Description
D9
ROWREL[15:0]
PWRMIN[15:0]
COLREL[15:0]
FWDTW[15:0]
REVTW[15:0]
ROW0[15:0]
ROW1[15:0]
ROW2[15:0]
ROW3[15:0]
ROW2[15:0]
HOTL[15:0]
COL2[15:0]
COL[15:0]
D8
D7
D6
D5
D4
D3
D2
Reference
D1
Page
38
38
D0