SI3211 ETC, SI3211 Datasheet - Page 42

• Manufacturer Part Number: SI3211
• Description: PROSLIC PROGRAMMABLE CMOS SLIC/CODEC WITH RINGING/BATTERY VOLTAGE GENERATION
• Manufacturer: ETC

Si 3210/ Si3 211/S i32 12
Two-Wire Impedance Matching
The ProSLIC provides on-chip programmable two-wire
impedance settings to meet a wide variety of worldwide
two-wire return loss requirements. The two-wire
impedance is programmed by loading one of the eight
available impedance values into the TISS[2:0] bits of the
Two-Wire Impedance Synthesis Control register (direct
Register 10). If direct Register 10 is not user-defined,
the default setting of 600
register.
Real and complex two-wire impedances are realized by
internal feedback of a programmable amplifier (RAC) a
switched
transconductance amplifier (G
creates the real portion and XAC creates the imaginary
portion of G
models the desired impedance value to the subscriber
loop. The differential ac current is fed to the subscriber
loop via the ITIPP and IRINGP pins through an off-chip
current buffer (I
transistor Q1 and Q2 (see Figure on page 16). G
referenced to an off-chip resistor (R
42
receive path.
An additional analog loopback (ALM1) takes the
digital stream at the output of the A/D converter and
feeds it back to the D/A converter. (See Figure 23.)
The signal path starts with the analog signal at the
input of the transmit path and ends with an analog
signal at the output of the receive path. This
loopback option allows the testing of the analog
signal processing circuitry of the Si3210 completely
independent from any activity in the DSP.
The full digital loopback tests almost all the circuitry
of both the transmit and receive paths. The analog
signal at the output of the receive path is fed back to
the input of the transmit path by way of the hybrid
filter path. (See Figure 23.) The signal path starts
with 8-bit PCM data input to the receive path and
ends with 8-bit PCM data at the output of the
transmit path. The user can bypass the companding
process and interface directly to the 16-bit data.
An additional digital loopback (DLM) takes the digital
stream at the input of the D/A converter in the
receive path and feeds it back to the transmit A/D
digital filter. The signal path starts with 8-bit PCM
data input to the receive path and ends with 8-bit
PCM data at the output of the transmit path. This
loopback option allows the testing of the digital
signal processing circuitry of the Si3210 completely
independent from any analog signal processing
activity.The user can bypass the companding
process and interface directly to the 16-bit data.
capacitor
m
’s input. G
BUF
), which is implemented using
m
network
then creates a current that
will be loaded into the TISS
m
). (See Figure 23.) RAC
15
(XAC)
).
Preliminary Rev. 1.11
and
m
is
a
The ProSLIC also provides a means to compensate for
degraded
excessive line capacitance (leakage). The CLC[1:0] bits
of direct Register 10 increase the ac signal magnitude
to compensate for the additional loss at the high end of
the audio frequency range. The default setting of
CLC[2:0] assumes no line capacitance.
Silicon revisions C and higher support the option to
remove the internal reference resistor used to
synthesize ac impedances for 600 + 2.16 F and
900 + 2.16 F settings so that an external resistor
reference may be used. This option is enabled by
setting ZSEXT = 1 (direct Register 108, bit 4).
Clock Generation
The ProSLIC will generate the necessary internal clock
frequencies from the PCLK input. PCLK must be
synchronous to the 8 kHz FSYNC clock and run at one
of the following rates: 256 kHz, 512 kHz, 768 kHz,
1.024 MHz, 1.536 MHz, 2.048 MHz, 4.096 MHz or
8.192 MHz. The ratio of the PCLK rate to the FSYNC
rate is determined via a counter clocked by PCLK. The
three-bit ratio information is automatically transferred
into an internal register, PLL_MULT, following a reset of
the ProSLIC. The PLL_MULT is used to control the
internal PLL which multiplies PCLK as needed to
generate 16.384 MHz rate needed to run the internal
filters and other circuitry.
The PLL clock synthesizer settles very quickly following
power up. However, the settling time depends on the
PCLK frequency and it can be approximately predicted
by the following equation:
Interrupt Logic
The ProSLIC is capable of generating interrupts for the
following events:
Loop current/ring ground detected
Ring trip detected
Power alarm
DTMF digit detected (Si3210 and Si3211 only)
Active timer 1 expired
Inactive timer 1 expired
Active timer 2 expired
Inactive timer 2 expired
Ringing active timer expired
Ringing inactive timer expired
Pulse metering active timer expired
Pulse metering inactive timer expired
subscriber
T
SETTLE
loop
=
---------------- -
F
PCLK
64
conditions
involving