ISL54200EVAL1Z Intersil, ISL54200EVAL1Z Datasheet - Page 18

• Manufacturer Part Number: ISL54200EVAL1Z
• Description: EVALUATION BOARD FOR ISL54200
• Manufacturer: Intersil

Specifications of ISL54200EVAL1Z

• Main Purpose: Interface, 2:1 Multiplexer
• Embedded: No
• Utilized Ic / Part: ISL54200
• Primary Attributes: 2 x SPDT Analog Switch
• Secondary Attributes: 2.7 V ~ 5.5 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Thin Dual Flat No-Lead Plastic Package (TDFN)
(DATUM A)
NX (b)
INDEX
AREA
5
(DATUM B)
SECTION "C-C"
6
8
INDEX
NX L
AREA
SEATING
6
PLANE
A
C
1
N
BOTTOM VIEW
(A1)
SIDE VIEW
N-1
TOP VIEW
e
(Nd-1)Xe
2
REF.
D2
D
D2/2
18
FOR ODD TERMINAL/SIDE
C C
e
7
NX b
C L
2X
A3
5
E2/2
0.10
8
0.10
E
B
A
NX k
E2
C
2X
M
A
TERMINAL TIP
//
0.10
C
L1
0.10
A
0.08
C B
B
C
C
9 L
ISL54200
ISL54200
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
6. The configuration of the pin #1 identifier is optional, but must be
7. Dimensions D2 and E2 are for the exposed pads which provide
8. Nominal dimensions are provided to assist with PCB Land
9. Compliant to JEDEC MO-229-WEED-3 except for D2
SYMBOL
( 2.90 )
between 0.15mm and 0.30mm from the terminal tip.
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
improved electrical and thermal performance.
Pattern Design efforts, see Intersil Technical Brief TB389.
dimensions.
A1
A3
D2
E2
Nd
A
D
E
N
b
e
k
L
Pin 1
(1.50)
TYPICAL RECOMMENDED LAND PATTERN
(8x 0.50)
0.70
0.20
2.95
2.25
2.95
1.45
0.25
0.25
MIN
-
MILLIMETERS
NOMINAL
0.50 BSC
0.20 REF
( 2.00 )
0.75
0.25
2.30
1.50
0.30
( 2.30 )
3.0
3.0
10
5
-
-
MAX
0.80
0.05
0.30
3.05
2.35
3.05
1.55
0.35
-
( 10X 0.25)
( 10X 0.50)
June 17, 2010
Rev. 4 8/09
NOTES
FN6408.2
5, 8
7, 8
7, 8
8
2
3
-
-
-
-
-
-
-