SI3216PPQ1-EVB Silicon Laboratories Inc, SI3216PPQ1-EVB Datasheet - Page 19
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3216PPQ1-EVB
Manufacturer Part Number
SI3216PPQ1-EVB
Description
BOARD EVAL W/SI3201 INTERFACE
Manufacturer
Silicon Laboratories Inc
Series
ProSLIC®r
Datasheets
1.SI3216-C-FT.pdf
(122 pages)
2.SI3216PPQX-EVB.pdf
(40 pages)
3.SI3216PPQ1-EVB.pdf
(122 pages)
Specifications of SI3216PPQ1-EVB
Main Purpose
Interface, Analog Front End (AFE)
Utilized Ic / Part
Si3216
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Table 12. Switching Characteristics—PCM Highway Serial Interface
V
Parameter
PCLK Frequency
PCLK Duty Cycle Tolerance
PCLK Period Jitter Tolerance
Rise Time, PCLK
Fall Time, PCLK
Delay Time, PCLK Rise to DTX Active
Delay Time, PCLK Rise to DTX
Transition
Delay Time, PCLK Rise to DTX Tri-state
Setup Time, FSYNC to PCLK Fall
Hold Time, FSYNC to PCLK Fall
Setup Time, DRX to PCLK Fall
Hold Time, DRX to PCLK Fall
Notes:
D
= 3.13 to 5.25 V, T
1. All timing is referenced to the 50% level of the waveform. Input test levels are V
2. Spec applies to PCLK fall to DTX tri-state when that mode is selected (TRI = 0).
SCLK
SDO
SDI
CS
A
= 0 to 70 °C for K-Grade, –40 to 85 °C for B-Grade, C
t
su1
t
d1
t
r
Figure 9. SPI Timing Diagram
2
Symbol
Preliminary Rev. 0.91
t
1/t
t
t
t
jitter
t
t
t
t
t
su1
su2
dty
t
d1
d2
d3
h1
h2
t
r
f
c
t
su2
t
t
c
thru
Conditions
t
d2
t
Test
h2
L
= 20 pF
Min
–120
—
—
—
—
—
—
—
—
40
—
—
—
—
—
25
20
25
20
1
IH –
V
t
I/O –
r
Typ
0.256
0.512
0.768
1.024
1.536
2.048
4.096
8.192
t
h1
50
—
—
—
—
—
—
—
—
—
—
0.4 V, V
1
IL
t
cs
= 0.4 V.
Max
t
120
d3
—
—
—
—
—
—
—
—
60
25
25
20
20
20
—
—
—
—
Si3216
1
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
%
19
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