LMV1089RLEVAL National Semiconductor, LMV1089RLEVAL Datasheet - Page 17

• Manufacturer Part Number: LMV1089RLEVAL
• Description: BOARD EVALUATION LMV1089
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LMV1089RLEVAL

• Main Purpose: Audio, Microphone Amp
• Embedded: No
• Utilized Ic / Part: LMV1089
• Primary Attributes: Dual Input, Single Output
• Secondary Attributes: Graphical User Interface, I²C Interface
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Example 2
An application using microphones with 10mV
output voltage, and a baseband chip after the LMV1089 with
3.3V
For optimum noise performance we would like to have the
maximum gain at the input stage.
1.
2.
3.
4.
5.
So using preamp gain = 34dB and postamp gain = 6dB is
optimum for this application.
Unprocessed Output Pins
The LMV1089 provides two single ended output pins
M1_UNP and M2_UNP. These pins provide the amplified
output signal from the two differential microphone input am-
plifiers Mic1 and Mic2. When the application containing the
LMV1089 is in a calibrated state the output level of the two
microphone paths are matched. This makes these outputs
suitable for stereo applications like video camera webcams
and photo cameras. Low cost microphones with wider gain
tolerance can be used because gain differences of the mi-
crophones will be compensated by the calibration system of
the LMV1089. In this situation the default gain of the Pre Am-
plifiers is set by GA0 and GA1 as described in
gain can be changed via I
in the I
I
I
The LMV1089 pin Serial Clock (SCL) pin is used for the I
clock and the Serial Data (SDA) pin is used for the I
Both these signals need a pull-up resistor according to I
specification. The LMV1089 can be controlled through two
slave addresses. The digital I
address for LMV1089 as shown
I
The data on SDA line must be stable during the HIGH period
of the clock signal (SCL). In other words, the state of the data
line can only be changed when SCL is LOW.
2
1
Address
I
Adress='0'
2
Address
I
Adress='1'
2
2
2
2
C SIGNALS
C DATA VALIDITY
st
nd
C
C
C Compatible Interface
Chip
Chip
P-P
10mV
This is lower than the maximum 1.4V
The NCP can have a maximum processing gain of 9dB
(depending on the calibration result) which will result in
3.5V
then maximum level that is allowed at the input of the
Post Amp of the LMV1089. Therefore the Pre Amp gain
has to be reduced, to 1.4V
limits the Pre Amp gain to a maximum of 34dB.
With a Post Amp gain setting of 6dB the output of the
Post Amp will be 2.8V
The nearest lower Post Amp gain will be 6dB.
2
C Compatible Interface section.
maximum input voltage.
P-P
P-P
at the output of the LMV1089. This level is higher
+ 36dB = 631mV
D7
1
1
TABLE 4. Chip Address
D6
1
1
2
C by writing register A as described
P-P
D5
0
0
2
which is OK for the baseband.
C address pin selects the I
P-P
P-P
inTable 4
D4 D3
.
0
0
minus 9dB = 0.5V
1
1
P-P
.
D2
1
1
so this is OK.
P-P
Table
D1
0
1
maximum
P-P
2
C data.
2. This
W/R
W/R
. This
D0
2
2
2
C
C
C
17
I
START and STOP bits classify the beginning and the end of
the I
fined as the SDA signal transitioning from HIGH to LOW while
SCL line is HIGH. STOP condition is defined as the SDA tran-
sitioning from LOW to HIGH while SCL is HIGH. The I
master always generates START and STOP bits. The I
is considered to be busy after START condition and free after
STOP condition. During data transmission, I
generate repeated START conditions. First START and re-
peated START conditions are equivalent,
10)
Note 10: The master should issue STOP after no acknowledgment.
TRANSFERRING DATA
Every byte put on the SDA line must be eight bits long, with
the most significant bit (MSB) being transferred first. Each
byte of data has to be followed by an acknowledge bit. The
acknowledge related clock pulse is generated by the master.
The transmitter releases the SDA line (HIGH) during the ac-
knowledge clock pulse. The receiver must pull down the SDA
line during the 9
(ACK). A receiver which has been addressed must generate
an acknowledge after each byte has been received.
After the START condition, the I
dress. This address is seven bits long followed by an eighth
bit which is a data direction bit (R/W). The LMV1089 address
is 11001100
a WRITE and a “1” indicates a READ. The second byte se-
lects the register to which the data will be written. The third
byte contains data to write to the selected register.
2
C START AND STOP CONDITIONS
2
C data transmission session. START condition is de-
2
or 11001110
I
I
2
2
th
C Start Stop Conditions
C Signals: Data Validity
clock pulse, signifying an acknowledge
I
2
C Chip Address
2
. For the eighth bit, a “0” indicates
2
C master sends a chip ad-
function-wise.(Note
2
C master can
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300472q1
300472q3
300472q2
2
C bus
2
C