SI5325/26-EVB Silicon Laboratories Inc, SI5325/26-EVB Datasheet
SI5325/26-EVB
Specifications of SI5325/26-EVB
Related parts for SI5325/26-EVB
SI5325/26-EVB Summary of contents
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Features Generates any frequency from 2 kHz to 945 MHz and select frequencies to 1.4 GHz from ...
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Si5326 Functional Block Diagram CKIN1 ÷ N31 CKIN2 ÷ N32 Xtal/Refclock Loss of Signal/ Frequency Offset Signal Detect Loss of Lock 2 Xtal or Refclock Hitless Switching Mux ® DSPLL ÷ N1_HS ÷ N2 Control I 2 C/SPI Port Clock ...
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T C ABLE O F ONTENTS 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Si5326 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Ambient Temperature T A Supply Voltage during V DD Normal Operation Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply ...
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Table 2. DC Characteristics (V = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol 1 Supply Current CKINn Input Pins Input Common Mode V ICM Voltage (Input Thresh- old Voltage) Input Resistance ...
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Si5326 Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Differential Output CKO VD Swing Single Ended Output CKO VSE Swing Differential Output CKO VD Voltage Common Mode Output ...
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Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Output Drive Current CKO IO (CMOS driving into CKO for output low VOL or CKO for output VOH high. CKOUT+ ...
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Si5326 Table 2. DC Characteristics (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol 4 3-Level Input Pins Input Voltage Low V ILL Input Voltage Mid V IMM Input Voltage High V IHH ...
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Table 3. Microprocessor Control (V = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Bus Lines (SDA, SCL) Input Voltage Low VIL I2C Input Voltage High VIH I2C Input Current II I2C ...
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Si5326 Table 3. Microprocessor Control (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol SPI Specifications Duty Cycle, SCLK t DC Cycle Time, SCLK t c Rise Time, SCLK t r Fall Time, ...
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Table 4. AC Specifications (V = 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Single-Ended Reference Clock Input Pin XA (XB with cap to GND) Input Resistance XA RIN Input Voltage Swing XA VPP Differential ...
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Si5326 Table 4. AC Specifications (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol Output Rise/Fall CKO TRF (20–80%) @ 212.5 MHz output Output Duty Cycle CKO DC Uncertainty @ 622.08 MHz LVCMOS ...
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Table 4. AC Specifications (Continued 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10 Parameter Symbol PLL Performance (fin=fout = 622.08 MHz; BW=120 Hz; LVPECL) Lock Time t LOCKMP Output Clock Phase t P_STEP Change Closed ...
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Si5326 Table 5. Jitter Generation Parameter Symbol Measurement Jitter Gen JGEN 0.02–80 MHz OC-192 4–80 MHz 0.05–80 MHz Jitter Gen JGEN 0.12–20 MHz OC-48 *Note: Test conditions: 1. fIN = fOUT = 622.08 MHz 2. Clock input: LVPECL 3. Clock ...
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Table 7. Absolute Limits Parameter DC Supply Voltage LVCMOS Input Voltage CKINn Voltage Level Limits XA/XB Voltage Level Limits Operating Junction Temperature Storage Temperature Range ESD HBM Tolerance (100 pF, 1.5 k); All pins except CKIN+/CKIN– ESD MM Tolerance; All ...
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Si5326 2. Typical Phase Noise Performance SONET_OC48, 12 kHz to 20 MHz SONET_OC192_A, 20 kHz to 80 MHz SONET_OC192_B, 4 MHz to 80 MHz SONET_OC192_C, 50 kHz to 80 MHz Brick Wall_800 MHz *Note: Jitter integration bands ...
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... Option 1: Crystal Crystal/Ref Clk Rate Option 2: Refclk+ Refclk– Control Mode (H) Reset Figure 5. Si5326 Typical Application Circuit (SPI Control Mode) Note: For an example schematic and layout, refer to the Si5325/26-EVB User’s Guide µF 4 System C 0.1 µF 1 Power Ferrite Supply ...
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Si5326 4. Functional Description ÷ N31 CKIN1 CKIN2 ÷ N32 Xtal/Refclock Loss of Signal/ Frequency Offset Signal Detect Loss of Lock The Si5326 is a jitter-attenuating precision clock multiplier for applications requiring sub 1 ps jitter performance. The Si5326 accepts ...
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The Si5326 has two differential clock outputs. The electrical format of each clock output is independently programmable to support LVPECL, LVDS, CML, or CMOS loads. If not required, the second clock output can be powered down to minimize power consumption. ...
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Si5326 5. Register Map All register bits that are not defined in this map should always be written with the specified Reset Values. The writing to these bits of values other than the specified Reset Values may result in undefined ...
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Register N2_HS[2: 128 129 130 CLAT- DIGHOLD- PROGRESS VALID 131 132 134 135 PARTNUM_RO[3:0] 136 RST_REG ICAL 138 139 142 143 ...
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Si5326 6. Register Descriptions Register 0. Bit D7 D6 FREE_ Name RUN R R/W Type Reset value = 0001 0100 Bit Name 7 Reserved Reserved. 6 FREE_RUN Free Run. Internal to the device, route XA/XB to CKIN2. This allows the ...
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Register 1. Bit D7 D6 Reserved Name R Type Reset value = 1110 0100 Bit Name 7:4 Reserved Reserved. 3:2 CK_PRIOR2 CK_PRIOR 2. [1:0] Selects which of the input clocks will be 2nd priority in the autoselection state machine. 00: ...
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Si5326 Register 3. Bit D7 D6 CKSEL_REG [1:0] Name R/W Type Reset value = 0000 0101 Bit Name 7:6 CKSEL_REG CKSEL_REG. [1:0] If the device is operating in register-based manual clock selection mode (AUTOSEL_REG = 00), and CKSEL_PIN = 0, ...
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Register 4. Bit D7 D6 AUTOSEL_REG [1:0] Name R/W Type Reset value = 0001 0010 Bit Name 7:6 AUTOSEL_ AUTOSEL_REG [1:0] REG [1:0] Selects method of input clock selection to be used. 00: Manual (either register or pin controlled, see ...
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Si5326 Register 6. Bit D7 D6 Reserved SLEEP Name R R/W Type Reset value = 0010 1101 Bit Name 7 Reserved Reserved. 6 SLEEP SLEEP. In sleep mode, all clock outputs are disabled and the maximum amount of internal cir- ...
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Register 7. Bit D7 D6 Name Type Reset value = 0010 1010 Bit Name 7:3 Reserved. Reserved. 2:0 FOSREFSEL FOSREFSEL [2:0]. [2:0] Selects which input clock is used as the reference frequency for frequency offset (FOS) alarms. 000: XA/XB (External ...
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Si5326 Register 8. Bit D7 D6 HLOG_2[1:0] Name R/W Type Reset value = 0000 0000 Bit Name 7:6 HLOG_2 [1:0] HLOG_2 [1:0]. 00: Normal operation 01: Holds CKOUT2 output at static logic 0. Entrance and exit from this state will ...
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Register 10. Bit D7 D6 Reserved Name R Type Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3 DSBL2_REG DSBL2_REG. This bit controls the powerdown of the CKOUT2 output buffer. If disable mode is selected, the N2_LS output ...
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Si5326 Register 11. Bit D7 D6 Name Type Reset value = 0100 0000 Bit Name 7:2 Reserved Reserved. 1 PD_CK2 PD_CK2. This bit controls the powerdown of the CKIN2 input buffer. 0: CKIN2 enabled 1: CKIN2 disabled 0 PD_CK1 PD_CK1. ...
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Register 17. Bit D7 D6 FLAT_ Name VALID R/W Type Reset value = 1000 0000 Bit Name 7 FLAT_VALID FLAT_VALID. Before writing a new FLAT[14:0] value, this bit must be set to zero, which causes the existing FLAT[14:0] value to ...
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Si5326 Register 19. Bit D7 D6 FOS_EN FOS_THR [1:0] Name R/W R/W Type Reset value = 0010 1100 Bit Name 7 FOS_EN FOS_EN. Frequency Offset Enable globally disables FOS. See the individual FOS enables (FOSX_EN, register 139). 0: FOS disable ...
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Register 20. Bit D7 D6 Reserved Name R Type Reset value = 0011 1110 Bit Name 7:4 Reserved Reserved. 3 CK2_BAD_ CK2_BAD_PIN. PIN The CK2_BAD status can be reflected on the C2B output pin. 0: C2B output pin tristated 1: ...
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Si5326 Register 21. Bit D7 D6 INCDEC_ Name PIN R/W Force 1 Type Reset value = 1111 1111 Bit Name 7 INCDEC_PIN INCDEC_PIN. Determines how coarse skew adjustments can be made. The adjustments can be made via hardware using the ...
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Register 22. Bit D7 D6 Reserved Name R Type Reset value = 1101 1111 Bit Name 7:4 Reserved Reserved. 3 CK_ACTV_ CK_ACTV_POL. POL Sets the active polarity for the CS_CA signals when reflected on an output pin. 0: Active low ...
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Si5326 Register 23. Bit D7 D6 Name Type Reset value = 0001 1111 Bit Name 7:3 Reserved Reserved. 2 LOS2_MSK LOS2_MSK. Determines if a LOS on CKIN2 (LOS2_FLG) is used in the generation of an interrupt. Writes to this register ...
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Register 24. Bit D7 D6 Name Type Reset value = 0011 1111 Bit Name 7:3 Reserved Reserved. 2 FOS2_MSK FOS2_MSK. Determines if the FOS2_FLG is used in the generation of an interrupt. Writes to this reg- ister do not change ...
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Si5326 Register 25. Bit D7 D6 N1_HS [2:0] Name R/W Type Reset value = 0010 0000 Bit Name 7:5 N1_HS [2:0] N1_HS [2:0]. Sets value for N1 high speed divider which drives NCn_LS ( low-speed divider. ...
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Register 32. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 NC1_LS NC1_LS [15:8]. [15:8] Sets value for NC1 low-speed divider, which drives CKOUT1 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 ...
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Si5326 Register 34. Bit D7 D6 Reserved Name R Type Reset value = 0000 0000 Bit Name 7:4 Reserved Reserved. 3:0 NC2_LS NC2_LS [19:16]. [19:16] Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. ...
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Register 36. Bit D7 D6 Name Type Reset value = 0011 0001 Bit Name 7:0 NC2_LS [7:0] NC2_LS [7:0]. Sets value for NC2 low-speed divider, which drives CKOUT2 output. Must odd. 00000000000000000000 = 1 00000000000000000001 = 2 ...
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Si5326 Register 40. Bit D7 D6 N2_HS [2:0] Name R/W Type Reset value = 1100 0000 Bit Name 7:5 N2_HS [2:0] N2_HS [2:0]. Sets value for N2 high speed divider, which drives N2LS low-speed divider. 000: 4 001: 5 010: ...
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Register 41. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N2_LS [15:8] N2_LS [15:8]. Sets value for N2 low-speed divider, which drives phase detector. 00000000000000000001 = 2 00000000000000000011 = 4 00000000000000000101 = 6 ... 11111111111111111111 ...
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Si5326 Register 43. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:3 Reserved Reserved. 2:0 N31 [18:16] N31 [18:16]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... ...
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Register 45. Bit D7 D6 Name Type Reset value = 0000 1001 Bit Name 7:0 N31_[7:0 N31_[7:0]. Sets value for input divider for CKIN1. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider values=[1, ...
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Si5326 Register 47. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 N32_[15:8] N32_[15:8]. Sets value for input divider for CKIN2. 0000000000000000000 = 1 0000000000000000001 = 2 0000000000000000010 = 3 ... 1111111111111111111 = 2^19 Valid divider ...
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Register 55. Bit D7 D6 Reserved Name R Type Reset value = 0000 0000 Bit Name 7:6 Reserved Reserved. 5:3 CLKIN2RATE CLKIN2RATE[2:0]. [2:0] CKINn frequency selection for FOS alarm monitoring. 000 MHz 001 MHz ...
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Si5326 Register 128. Bit D7 D6 Name Type Reset value = 0010 0000 Bit Name 7:2 Reserved Reserved. 1 CK2_ACTV_ CK2_ACTV_REG. REG Indicates if CKIN2 is currently the active clock for the PLL input. 0: CKIN2 is not the active ...
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Register 129. Bit D7 D6 Name Type Reset value = 0000 0110 Bit Name 7:3 Reserved Reserved. 2 LOS2_INT LOS2_INT. Indicates the LOS status on CKIN2. 0: Normal operation. 1: Internal loss-of-signal alarm on CKIN2 input. 1 LOS1_INT LOS1_INT. Indicates ...
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Si5326 Register 130. Bit D7 D6 CLAT- DIGHOLD- Name PROGRESS VALID R R Type Reset value = 0000 0001 Bit Name 7 CLAT- CLAT Progress. PROGRESS Indicates if the last change in the CLAT register has been processed. 0: Coarse ...
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Register 131. Bit D7 D6 Name Type Reset value = 0001 1111 Bit Name 7:3 Reserved Reserved. 2 LOS2_FLG CKIN2 Loss-of-Signal Flag. 0: Normal operation. 1: Held version of LOS2_INT. Generates active output interrupt if output interrupt pin is enabled ...
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Si5326 Register 132. Bit D7 D6 Reserved Name R Type Reset value = 0000 0010 Bit Name 7:4 Reserved Reserved. 3 FOS2_FLG CLKIN_2 Frequency Offset Flag. 0: Normal operation. 1: Held version of FOS2_INT. Generates active output interrupt if output ...
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Register 134. Bit D7 D6 Name Type Reset value = 0000 0001 Bit Name 7:0 PARTNUM_ Device 2). RO [11:0] 0000 0001 1010: Si5326 Register 135. Bit D7 D6 PARTNUM_RO [3:0] Name R Type Reset value = ...
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Si5326 Register 136. Bit D7 D6 RST_REG ICAL Name R/W R/W Type Reset value = 0000 0000 Bit Name 7 RST_REG Internal Reset (Same as Pin Reset). Note: The I 0: Normal operation. 1: Reset of all internal logic. Outputs ...
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Register 138. Bit D7 D6 Name Type Reset value = 0000 1111 Bit Name 7:2 Reserved Reserved. 1 LOS2_EN Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). [1:0] Note: LOS2_EN is split between two registers. 00: Disable ...
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Si5326 Register 139. Bit D7 D6 Reserved Name R Type Reset value = 1111 1111 Bit Name 7:6 Reserved Reserved. 5 LOS2_EN Enable CKIN2 LOS Monitoring on the Specified Input (2 of 2). [1:0] Note: LOS2_EN is split between two ...
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Register 142. Bit D7 D6 Name Type Reset value = 0000 0000 Bit Name 7:0 INDEPEND- INDEPENDENTSKEW1. ENTSKEW1 Eight-bit field that represents a 2’s complement of the phase offset in terms of clocks from [7:0] the high speed output divider. ...
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Si5326 7. Pin Descriptions: Si5326 RST NC INT_C1B C2B VDD XA XB GND NC Pin # Pin Name I/O Signal Level 1 I LVCMOS RST 2, 9, 14, NC — 30 INT_C1B O LVCMOS Note: Internal register names ...
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Pin # Pin Name I/O Signal Level 4 C2B O LVCMOS 5, 10 Supply Analog GND Supply GND 11 RATE0 I 3-Level 15 RATE1 16 CKIN1+ I Multi ...
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Si5326 Pin # Pin Name I/O Signal Level 18 LOL O LVCMOS 19 DEC I LVCMOS 20 INC I LVCMOS Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. See Section “5.Register Map”. 60 Description PLL Loss of ...
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Pin # Pin Name I/O Signal Level 21 CS_CA I/O LVCMOS 22 SCL I LVCMOS 23 SDA_SDO I/O LVCMOS LVCMOS A2_SS I LVCMOS 27 SDI I LVCMOS Note: Internal register names are indicated by ...
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Si5326 Pin # Pin Name I/O Signal Level 29 CKOUT1– O Multi 28 CKOUT1+ 34 CKOUT2– O Multi 35 CKOUT2+ 36 CMODE I LVCMOS GND PAD GND GND Supply Note: Internal register names are indicated by underlined italics, e.g., INT_PIN. ...
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Table 9 lists all of the register locations that should be followed by an ICAL after their contents are changed. Table 9. Register Locations Requiring ICAL Addr Register 0 BYPASS_REG 0 CKOUT_ALWAYS_ON 1 CK_PRIOR2 1 CK_PRIOR1 2 BWSEL_REG 4 HIST_DEL ...
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Si5326 64 Table 10. Si5326 Pull up/Pull down Pin # Si5326 Pull up/ Pull down 1 RST U 11 RATE0 RATE1 DEC D 20 INC D 21 CS_CA SCL D 24 ...
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... Range Si5326A-C-GM 2 kHz–945 MHz 970–1134 MHz 1.213–1.4 GHz Si5326B-C-GM 2 kHz–808 MHz Si5326C-C-GM 2 kHz–346 MHz Si5325/26-EVB Note: Add the end of the device to denote tape and reel options. Package ROHS6, Pb-Free 36-Lead QFN Yes 36-Lead QFN Yes 36-Lead QFN ...
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Si5326 9. Package Outline: 36-Pin QFN Figure 7 illustrates the package details for the Si5326. Table 11 lists the values for the dimensions shown in the illustration. Figure 7. 36-Pin Quad Flat No-lead (QFN) Symbol Millimeters Min Nom A 0.80 ...
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Recommended PCB Layout Figure 9. Ground Pad Recommended Layout Figure 8. PCB Land Pattern Diagram Rev. 1.0 Si5326 67 ...
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Si5326 Table 12. PCB Land Pattern Dimensions Dimension Notes (General): 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI ...
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Si5326 Device Top Mark Laser Mark Method: 0.80 mm Font Size: Right-Justified Si5326Q Line 1 Marking: C-GM Line 2 Marking: YYWWRF Line 3 Marking: Pin 1 Identifier Line 4 Marking: XXXX Customer Part Number Q = Speed Code: A, ...
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Si5326 OCUMENT HANGE IST Revision 0.1 to Revision 0.2 Updated LVTTL to LVCMOS is Table 2, “Absolute Maximum Ratings,” on page 6. Added Figure 3, “Typical Phase Noise Plot,” on page 16. Updated Figure 4, ...
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N : OTES Rev. 1.0 Si5326 71 ...
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