WAVEVSN BRD 5.1/NOPB National Semiconductor, WAVEVSN BRD 5.1/NOPB Datasheet - Page 8

• Manufacturer Part Number: WAVEVSN BRD 5.1/NOPB
• Description: BOARD INTERFACE DIGITAL HI SPD
• Manufacturer: National Semiconductor
• Series: WaveVisionr

Specifications of WAVEVSN BRD 5.1/NOPB

• Main Purpose: Interface, Data Capture
• Embedded: Yes, ASIC
• Primary Attributes: ADC & DAC Evaluation
• Secondary Attributes: Graphical User Interface, USB Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Utilized Ic / Part: -
• Other names: WAVEVSN BRD 5.1

2 System Functionality
2.1 System Block Diagram
Figure 2: WaveVision5 System Block Diagram (For ADCs)
2.2 General System Overview
2.2.1 ADC Evaluation Boards
The ADC evaluation board (shown in Figure 2) delivers conversion data along with a source-synchronous
clock to the Future Bus connector (J1) or to the high speed HMZd connector (U2). The data and clock signals
are connected directly to the FPGA Device (U1) on the WaveVision5 Data Capture Board. During data
capture, the FPGA captures the data from the ADC using the source-synchronous clock and routes it to the
designated destination. As shown in the figure, there are three possible destinations. If the data is to be
stored on the board before being forwarded to the PC, it first goes through a FIFO. After the FIFO, the data is
routed to either the FPGA’s internal memory or to external memory consisting of DDR SRAM ICs located on
the WaveVision5 Data Capture Board. Once the requested amount of data has been stored in either memory
location, it is uploaded to the PC through the FPGA’s USB interface and the Cypress Microcontroller (U19) for
analysis. The third path is to connectors on the board. Lower frequency data can be sent to the LSA
connector (J7). Higher frequency data can be sent to either the Mictor connector (J5) or SoftTouch connector
(J10), depending on the board’s configuration.
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