DS32512DK Maxim Integrated Products, DS32512DK Datasheet - Page 21
DS32512DK
Manufacturer Part Number
DS32512DK
Description
KIT DEMO FOR DS32512
Manufacturer
Maxim Integrated Products
Datasheet
1.DS32506N.pdf
(130 pages)
Specifications of DS32512DK
Main Purpose
Telecom, Line Interface Units (LIUs)
Utilized Ic / Part
DS32512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
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Table 7-6. Parallel Interface Pin Descriptions
RDY/ACK
WR/R/W
GPIOAn
GPIOBn
BSWAP
D[15:0]
A[10:1]
NAME
RD/DS
A[0] /
ALE
INT
CS
TYPE
I/Opd
I/Opd
I/O
Oz
Oz
I
I
I
I
I
I
Chip Select (Active Low). This pin must be asserted to read or write internal registers. See
Section 8.8.3.
Read Enable (Active Low)/Data Strobe (Active Low)
RD
DS
the
Write Enable (Active Low)/Read/Write Select
WR
R/W: For the Motorola-style bus
with
Address Latch Enable. This pin controls a latch on the A[10:0] inputs. For a nonmultiplexed
parallel bus, ALE is wired high to make the latch transparent. For a multiplexed parallel bus, the
falling edge of ALE latches the address. See Section 8.8.3.
Address Bus (Excluding LSB). These inputs specify the address of the internal 16-bit register
to be accessed. A10 is not present on the DS32506. See Section 8.8.
A[0]: This pin is connected to the lower address bit in 8-bit bus modes
0 = Output register bits 7:0 on D[7:0]; D[15:8] high impedance
1 = Output register bits 15:8 on D[7:0]; D[15:8] high impedance
BSWAP: This pin is tied high or low in 16-bit bus modes
0 = Output register bits 15:8 on D[15:8] and bits 7:0 on D[7:0]
1 = Output register bits 7:0 on D[15:8] and bits 15:8 on D[7:0]
Data Bus. A 8-bit or 16-bit bidirectional data bus. These pins are inputs during writes to internal
registers and outputs during reads. D[15:8] are disabled (high impedance) in 8-bit bus modes
(IFSEL
modes
high. See Section 8.8.
Ready Handshake (Tri-State)/Acknowledge Handshake (Tri-State, Active Low). Tri-stated
when
RDY: Intel Mode (IFSEL = 100 or 110): RDY goes high when the read or write cycle can
progress.
ACK
progress.
Interrupt Output (Active Low, Open Drain, or Push-Pull). This pin is driven low in response
to one or more unmasked, active interrupt sources within the device. INT remains low until the
interrupt is serviced or masked. When GLOBAL.CR2:INTM = 0,
inactive (default). When INTM = 1,
when
General-Purpose I/O A. When a microprocessor interface is enabled
the “A” general-purpose I/O pin for port n. See Section 8.7.3.
General-Purpose I/O B. When a microprocessor interface is enabled
the “B” general-purpose I/O pin for port n. See Section 8.7.3. Note: GPIOB1, GPIOB2, and
GPIOB3 can also be programmed as global control/status pins.
Address Bus LSB/Byte Swap. See Section 8.8.2.
: For the Motorola-style bus
: For the Intel-style bus
: For the Intel-style bus
R/W
R/W
: Motorola Mode (IFSEL = 101 or 111): ACK goes low when the read or write cycle can
CS
RST
(IFSEL
= 10X). D[15:0] are disabled (high impedance) when
pin specifies whether the access is a read or a write. See Section 8.8.3.
= 1 indicating a read and
= 1 or
= 0. See Section 8.10.
= 11X) the upper and lower bytes can be swapped by pulling the
RST
= 0. See Section 8.8.
(IFSEL
(IFSEL
21 of 130
(IFSEL
(IFSEL
= 1X0),
= 1X0),
INT
R/W
= 1X1),
is driven high when inactive.
= 1X1),
= 0 indicating a write. See Section 8.8.3.
FUNCTION
RD
WR
is asserted to read internal registers.
DS
is asserted to write internal registers.
R/W
is asserted to access internal registers while
determines the type of bus transaction,
(IFSEL
CS
= 11X).
INT
DS32506/DS32508/DS32512
= 1 or
is high impedance when
INT
(IFSEL
(IFSEL
(IFSEL
RST
is high impedance
= 0. In 16-bit bus
≠ 000), this pin is
≠ 000), this pin is
= 10X).
BSWAP
pin
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