DS32512DK Maxim Integrated Products, DS32512DK Datasheet - Page 60
DS32512DK
Manufacturer Part Number
DS32512DK
Description
KIT DEMO FOR DS32512
Manufacturer
Maxim Integrated Products
Datasheet
1.DS32506N.pdf
(130 pages)
Specifications of DS32512DK
Main Purpose
Telecom, Line Interface Units (LIUs)
Utilized Ic / Part
DS32512
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Secondary Attributes
-
Embedded
-
Primary Attributes
-
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Bit 2: CLAD Loss of Lock (CLOL). This bit is set when the CLAD is not locked to the reference frequency.
Bit 0: Global Performance Monitoring Update Status (GPMS). This bit is set when the PORT.SR:PMS status
bits are set in all of the ports that are enabled for global update control (i.e., all ports that have PORT.CR1:PMUM =
1). Ports that have PORT.CR1:PMUM = 0 have no effect on this bit. In global software update mode, the global
update request bit (GLOBAL.CR1:GPMU) should be held high until this status bit goes high. See Section 8.7.4.
Bit 6: CLAD C Clock Activity Latched (CLKCL). This bit is set when the signal on the
This bit should always be low when GLOBAL.CR2:CLAD[6:4] ≠ 000. See Section 8.7.1.
Bit 5: CLAD B Clock Activity Latched (CLKBL). This bit is set when the signal on the
This bit should always be low when GLOBAL.CR2:CLAD[6:4] ≠ 000. See Section 8.7.1.
Bit 4: CLAD A Clock Activity Latched (CLKAL). This bit is set when the signal on the
This bit should always be low when GLOBAL.CR2:CLAD[6:4] ≠ 000. See Section 8.7.1.
Bit 3: CLAD Reference Clock Activity Status Latched (CLADL). This bit is set when the CLAD PLL reference
clock signal on the
See Section 8.7.1.
Bit 2: CLAD Loss of Lock Latched (CLOLL). This bit is set when the GLOBAL.SR:CLOL status bit transitions
from low to high.
Bit 1: Global One-Second Status Latched (G1SREFL). This bit is set once each second when the internal global
one-second timer signal transitions low to high. When set, this bit causes an interrupt if interrupt enables
GLOBAL.SRIE:G1SREFIE and GLOBAL.ISRIE:GSRIE are both set. See Section 8.7.1.
Bit 0: Global Performance Monitoring Update Status Latched (GPMSL). This bit is set when the
GLOBAL.SR:GPMS status bit changes from low to high. When set, this bit causes an interrupt if interrupt enables
GLOBAL.SRIE:GPMSIE and GLOBAL.ISRIE:GSRIE are both set. See Section 8.7.1.
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Register Name:
Register Description:
Register Address:
Bit #
Name
Bit #
Name
0 = The associated update request signal is low or not all register updates are completed.
1 = The requested performance register updates are all completed.
15
—
15
—
—
—
—
—
7
7
REFCLK
CLKCL
pin is active. Note: When GLOBAL.CR2:CLAD[6:4] = 000, the
14
14
—
—
—
—
—
6
6
GLOBAL.SR
Global Status Register
028h
GLOBAL.SRL
Global Status Register Latched
02Ah
CLKBL
13
13
—
—
—
—
—
5
5
60 of 130
CLKAL
12
12
—
—
—
—
—
4
4
CLADL
11
11
—
—
—
—
—
3
3
CLOLL
CLOL
10
10
—
—
—
2
0
2
DS32506/DS32508/DS32512
CLKC
CLKB
CLKA
G1SREFL
REFCLK
—
—
—
—
—
9
1
9
1
pin is active. Note:
pin is active. Note:
pin is active. Note:
pin is unused.
GPMSL
GPMS
—
—
—
8
0
0
8
0
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