KDC5514-Q48EVAL Intersil, KDC5514-Q48EVAL Datasheet - Page 27

• Manufacturer Part Number: KDC5514-Q48EVAL
• Description: DAUGHTER CARD FOR KAD5514
• Manufacturer: Intersil
• Series: FemtoCharge™r

Specifications of KDC5514-Q48EVAL

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 250M
• Data Interface: Parallel
• Inputs Per Adc: 1 Differential
• Input Range: 1.47 Vpp
• Power (typ) @ Conditions: 429mW @ 250MSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: KAD5514P-25, KMB001 Motherboard
• For Use With: KMB001LEVAL - MOTHERBOARD FOR LVDS ADC CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Memory Map
VALUE
0000
0001
0010
0100
0101
1000
0011
0110
0111
26-5F
(Hex)
03-07
11-1F
Addr
00
01
02
08
09
10
20
21
22
23
24
25
device_index_A
offset_coarse
gain_medium
chip_version
gain_coarse
TABLE 15. OUTPUT TEST MODES
Parameter
port_config
offset_fine
Negative Full-Scale
burst_end
Positive Full-Scale
gain_fine
reserved
reserved
reserved
reserved
chip_id
modes
OUTPUT TEST
Name
Checkerboard
User Pattern
0xC0[3:0]
Reserved
Reserved
One/Zero
Midscale
MODE
Off
(MSB)
Active
27
Bit 7
SDO
user_patt1
WORD 1
0xAAAA
0xFFFF
0xFFFF
0x8000
0x0000
LSB First
N/A
N/A
Bit 6
Reserved
user_patt2
WORD 2
Reserved
Reset
0x5555
0x0000
TABLE 16. SPI MEMORY MAP
Bit 5
Soft
N/A
N/A
N/A
N/A
N/A
Reserved
KAD5514P
Burst end address [7:0]
Chip Version #
Bit 4
Coarse Offset
Medium Gain
Fine Offset
Fine Gain
Reserved
Reserved
Reserved
Reserved
Chip ID #
ADDRESS 0XC2: USER_PATT1_LSB
ADDRESS 0XC3: USER_PATT1_MSB
These registers define the lower and upper eight bits,
respectively, of the first user-defined test word.
ADDRESS 0XC2: USER_PATT2_LSB
ADDRESS 0XC3: USER_PATT2_MSB
These registers define the lower and upper eight bits,
respectively, of the second user-defined test word.
Bit 3
Mirror
(bit5)
Coarse Gain
Bit 2
Power-Down Mode [2:0]
001 = Normal Operation
other codes = reserved
000 = Pin Control
100 = Sleep
ADC01
010 = Nap
Mirror
Bit 1
(bit6)
ADC00
(LSB)
Mirror
Bit 0
(bit7)
affected by
Def. Value
Soft Reset
Read only
Read only
cal. value
cal. value
cal. value
cal. value
cal. value
(Hex)
NOT
00h
00h
00h
00h
September 10, 2009
Indexed/
Global
FN6804.2
G
G
G
G
I
I
I
I
I
I
I