EVAL-AD7650CBZ Analog Devices Inc, EVAL-AD7650CBZ Datasheet - Page 14

• Manufacturer Part Number: EVAL-AD7650CBZ
• Description: BOARD EVALUATION FOR AD7650
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7650CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 570k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 150mW @ 570kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7650
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7650
PARALLEL INTERFACE
The AD7650 is configured to use the parallel interface when the
SER/PAR is held low. The data can be read either after each
conversion, which is during the next acquisition phase, or dur-
ing the following conversion as shown, respectively, in Figure 11
and Figure 12. When the data is read during the conversion,
however, it is recommended that it is read only during the first
half of the conversion phase. That avoids any potential feed-
through between voltage transients on the digital interface and
the most critical analog conversion circuitry.
BUSY
DATA
BUS
RD
CS
t
12
SDOUT
CNVST
CS, RD
BUSY
SYNC
SCLK
CONVERSION
CURRENT
t
3
t
13
t
t
t
14
15
16
t
29
EXT/INT = 0
X
t
22
t
20
D15
1
t
19
t
18
RDC/SDIN = 0
D14
t
t
21
2
23
t
28
SERIAL INTERFACE
The AD7650 is configured to use the serial interface when the
SER/PAR is held high. The AD7650 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on SCLK pin. The output data is
valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7650 is configured to generate and provide the serial data
clock SCLK when the EXT/
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted if desired. Depending on RDC/SDIN input, the
data can be read after each conversion or during the following
conversion. Figure 13 and Figure 14 show the detailed timing
diagrams of these two modes.
CNVST,
CS = 0
BUSY
3
DATA
BUS
RD
INVSCLK = INVSYNC = 0
t
14
12
t
D2
3
CONVERSION
PREVIOUS
15
D1
t
1
t
INT
24
t
16
t
13
30
pin is held low. The AD7650
D0
t
4
t
t
t
25
26
27