EVAL-AD7660CBZ Analog Devices Inc, EVAL-AD7660CBZ Datasheet - Page 6

• Manufacturer Part Number: EVAL-AD7660CBZ
• Description: BOARD EVALUATION FOR AD7660
• Manufacturer: Analog Devices Inc
• Series: PulSAR®r

Specifications of EVAL-AD7660CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 200mW @ 100kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7660
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7660
Pin
No.
22
23
24
25–28
29
30
31
32
33
34
35
36
37
38
39
43
NOTES
AI = Analog Input
DI = Digital Input
DI/O = Bidirectional Digital
DO = Digital Output
P = Power
Mnemonic
D9
or SCLK
D10
or SYNC
D11
or RDERROR
D[12:15]
BUSY
DGND
RD
CS
RESET
PD
CNVST
AGND
REF
REFGND
INGND
IN
DO
Type
DI/O
DO
DO
DO
P
DI
DI
DI
DI
DI
P
AI
AI
AI
AI
Description
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this pin, part of the Serial Port, is used as a serial data clock input
or output, dependent upon the logic state of the EXT/INT pin. The active edge where the
data SDOUT is updated depends upon the logic state of the INVSCLK pin.
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH, this output, part of the Serial Port, is used as a digital output
frame synchronization for use with the internal data clock (EXT/INT = Logic LOW). When
a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and remains
HIGH while SDOUT output is valid. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid.
When SER/PAR is LOW, this output is used as the Bit 11 of the Parallel Port Data Output Bus.
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the Serial Port, is
used as an incomplete read error flag. In Slave Mode, when a data read is started and not
complete when the following conversion is complete, the current data is lost and RDERROR is
pulsed HIGH.
Bit 12 to Bit 15 of the Parallel Port Data Output Bus. These pins are always outputs regard-
less of the state of SER/PAR.
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the
conversion is complete and the data is latched into the on-chip shift register. The falling edge
of BUSY could be used as a data-ready clock signal.
Must Be Tied to Digital Ground
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled.
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is
enabled. CS is also used to gate the external clock.
Reset Input. When set to a logic HIGH, reset the AD7660. Current conversion, if any, is aborted.
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conver-
sions are inhibited after the current one is completed.
Start Conversion. If CNVST is HIGH when the acquisition phase (t
falling edge on CNVST puts the internal sample-and-hold into the hold state and initiates a
conversion. This mode is the most appropriate if low sampling jitter is desired. If CNVST is
LOW when the acquisition phase (t
hold state and a conversion is immediately started.
Must Be Tied to Analog Ground
Reference Input Voltage
Reference Input Analog Ground
Analog Input Ground
Primary Analog Input with a Range of 0 V to V
PIN FUNCTION DESCRIPTIONS (continued)
–6–
8
) is complete, the internal sample-and-hold is put into the
REF
8
) is complete, the next
REV. D