AD677-EB Analog Devices Inc, AD677-EB Datasheet - Page 13

• Manufacturer Part Number: AD677-EB
• Description: BOARD EVAL SAMPLING ADC AD677
• Manufacturer: Analog Devices Inc

Specifications of AD677-EB

• Rohs Status: RoHS non-compliant
• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 100k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: ±VREF
• Power (typ) @ Conditions: 450mW @ 100kSPS
• Voltage Supply Source: Analog and Digital, Dual ±
• Operating Temperature: 0°C ~ 70°C
• Utilized Ic / Part: AD677

The standard deviation of this distribution is approximately
0.5 LSBs. If less uncertainty is desired, averaging multiple con-
versions will narrow this distribution by the inverse of the square
root of the number of samples; i.e., the average of 4 conversions
would have a standard deviation of 0.25 LSBs.
DSP INTERFACE
Figure 10 illustrates the use of the Analog Devices ADSP-2101
digital signal processor with the AD677. The ADSP-2101 FO
(flag out) pin of Serial Port 1 (SPORT 1) is connected to the
SAMPLE line and is used to control acquisition of data. The
ADSP-2101 timer is used to provide precise timing of the FO
pin.
The SCLK pin of the ADSP-2101 SPORT0 provides the CLK
input for the AD677. The clock should be programmed to be
approximately 2 MHz to comply with AD677 specifications. To
minimize digital feedthrough, the clock should be disabled (by
setting Bit 14 in SPORT0 control register to 0) during data ac-
quisition. Since the clock floats when disabled, a pulldown resis-
tor of 12 k –15 k should be connected to SCLK to ensure it
will be LOW at the falling edge of SAMPLE. To maximize the
conversion rate, the serial clock should be enabled immediately
after SAMPLE is brought LOW (hold mode).
The AD677 BUSY signal is connected to RF0 to notify
SPORT0 when a new data word is coming. SPORT0 should be
configured in normal, external, noninverting framing mode and
can be programmed to generate an interrupt after the last data
bit is received. To maximize the conversion rate, SAMPLE
should be brought HIGH immediately after the last data bit is
received.
Figure 11. S/(N+D) and THD vs. V
tion is not guaranteed below +5 V
REV. A
106
102
98
94
90
86
82
SERIAL
PORT 0
2.5
ADSP-2101
Figure 10. ADSP-2101 Interface
3.5
SCLK0
RFS0
TFS0
S/(N+D)
DT0
DR0
4.5
FO
5.5
THD
V
REF
6.5
– Volts
REF
REF
7.5
, f
)
SAMPLE
CLK
BUSY
SDATA
S
= 100 kHz (Calibra-
8.5
AD677
9.5
10.0
–13–
–100
–120
–140
–100
–120
–140
–20
–40
–60
–80
–20
–40
–60
–80
Figure 12. S/(N+D) and THD vs. Input Amplitude,
f
Figure 13. 4096 Point FFT at 100 kSPS, f
V
Figure 14. 4096 Point FFT at 100 kSPS, f
V
S
0
0
REF
REF
0
= 100 kHz
0
105
100
90
80
70
60
50
40
30
20
10
= 5 V
= 10 V
–80
5
5
–70
10
10
–60
15
15
THD
–50
INPUT LEVEL – dB
20
20
FREQUENCY – kHz
FREQUENCY – kHz
–40
25
25
–30
30
30
S/(N+D)
–20
35
35
IN
IN
AD677
= 1 kHz,
= 1 kHz,
–10
40
40
45
45
0
48
50