AD9262-EBZ Analog Devices Inc, AD9262-EBZ Datasheet - Page 30
![BOARD EVALUATION FOR AD9262](/photos/24/6/240687/4667253_sml.jpg)
AD9262-EBZ
Manufacturer Part Number
AD9262-EBZ
Description
BOARD EVALUATION FOR AD9262
Manufacturer
Analog Devices Inc
Specifications of AD9262-EBZ
Design Resources
Interfacing ADL5382 to AD9262 as an RF-to-Bits Solution (CN0062)
Number Of Adc's
2
Number Of Bits
16
Sampling Rate (per Second)
160M
Data Interface
Serial, SPI™
Inputs Per Adc
1 Differential
Input Range
2 Vpp
Power (typ) @ Conditions
487mW @ 40MSPS
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD9262
Silicon Manufacturer
Analog Devices
Application Sub Type
ADC
Kit Application Type
Data Converter
Silicon Core Number
AD9262
Kit Contents
Software, Evaluation Board
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
AD9262
MEMORY MAP
Table 25. Memory Map
Register Name
SPI Port Config
Chip ID
Chip Grade
Channel Index
Power Modes
PLLENABLE
PLL
Analog Input
Output Modes
Output Adjust
Output Clock
Reference
Output Data
Overrange
QEC1
QEC2
MEMORY MAP DEFINITIONS
Table 26. Memory Map Definitions
Register
SPI Port Config
Chip ID
Chip Grade
Channel Index
Power Modes
PLLENABLE
PLL
Analog Input
Address
0x00
0x01
0x02
0x05
0x08
0x09
0x0A
0x0F
0x14
0x15
0x16
0x18
0x101
0x111
0x112
0x113
Address
0x00
0x01
0x02
0x05
0x08
0x09
0x0A
0x0F
Bit 7
0
PLLLOCKED
DRVSTD
DCOINV
AUTORST
Bit(s)
6, 1
5, 2
[7:0]
[5:4]
[1:0]
[1:0]
2
7
6
[5:0]
[6:5]
Mnemonic
LSBFIRST
SOFTRESET
CHIPID
CHILDID
Channel
PWRDWN
PLLENABLE
PLLLOCKED
PLLAUTO
PLLMULT
BW
Bit 6
LSBFIRST
PLLAUTO
EXTREF
QEC
OR_IND
1
BW[1:0]
Default
0
0
0x22
0
0
0
0
0
0
0
0
Rev. A | Page 30 of 32
Bit 5
SOFTRESET
Interleave
DCFRZ
CHILDID[2:0]
Description
0: serial interface uses MSB first format
1: serial interface uses LSB first format
1: default all serial registers except 0x00, 0x09, and 0x0A
0x22: AD9262
0x00: 10 MHz bandwidth
0x10: 5 MHz bandwidth
0x20: 2.5 MHz bandwidth
0: both channels addressed simultaneously
1: Channel A only addressed
2: Channel B only addressed
3: both channels addressed simultaneously
0x0: normal operation
0x1: power-down (local)
0x2: standby (everything except reference circuits)
0x3: sleep
1: enable PLL
0: PLL is not locked
1: PLL is locked
1: PLL autoband enabled
See Table 10
See Table 13
PHASEFRZ
Bit 4
1
OUTENB
CHIPID[7:0]
GAINFRZ
Bit 3
1
DRVSTR33[1:0]
ORTHRESH[5:0]
PLLMULT[5:0]
KOUT[5:0]
Bit 2
SOFTRESET
PLLENABLE
OUTINV
DCENB
DCFRC
PHASEENB
PHASEFRC
Bit 1
LSBFIRST
DRVSTR18[1:0]
Format[1:0]
PWRDWN[1:0]
Channel[1:0]
GAINENB
GAINFRC
Bit 0
0