ADC081S051EVAL National Semiconductor, ADC081S051EVAL Datasheet - Page 10

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ADC081S051EVAL

Manufacturer Part Number
ADC081S051EVAL
Description
BOARD EVALUATION FOR ADC081S051
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of ADC081S051EVAL

Number Of Adc's
1
Number Of Bits
8
Sampling Rate (per Second)
500k
Data Interface
Serial
Inputs Per Adc
1 Single Ended
Input Range
0 ~ 5.25 V
Power (typ) @ Conditions
8.5mW @ 500kSPS
Voltage Supply Source
Single Supply
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
ADC081S051
Lead Free Status / RoHS Status
Not applicable / Not applicable
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Applications Information
1.0 ADC081S051 OPERATION
The ADC081S051 is a successive-approximation analog-to-
digital converter designed around a charge-redistribution dig-
ital-to-analog converter core. Simplified schematics of the
ADC081S051 in both track and hold modes are shown in
Figure 3
in track mode: switch SW1 connects the sampling capacitor
to the input and SW2 balances the comparator inputs. The
device is in this state until CS is brought low, at which point
the device moves to hold mode.
Spectral Response, V
and
Figure
4, respectively. In
A
= 5V, f
Figure
SCLK
FIGURE 3. ADC081S051 in Track Mode
FIGURE 4. ADC081S051 in Hold Mode
3, the device is
= 10 MHz
20145570
10
Figure 4
nects the sampling capacitor to ground, maintaining the sam-
pled voltage, and switch SW2 unbalances the comparator.
The control logic then instructs the charge-redistribution DAC
to add or subtract fixed amounts of charge from the sampling
capacitor until the comparator is balanced. When the com-
parator is balanced, the digital word supplied to the DAC is
the digital representation of the analog input voltage. The de-
vice moves from hold mode to track mode on the 13th rising
edge of SCLK.
Power Consumption vs. Throughput,
shows the device in hold mode: switch SW1 con-
f
SCLK
20145509
20145510
= 10 MHz
20145555

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