ADC081S051EVAL National Semiconductor, ADC081S051EVAL Datasheet - Page 13

• Manufacturer Part Number: ADC081S051EVAL
• Description: BOARD EVALUATION FOR ADC081S051
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of ADC081S051EVAL

• Number Of Adc's: 1
• Number Of Bits: 8
• Sampling Rate (per Second): 500k
• Data Interface: Serial
• Inputs Per Adc: 1 Single Ended
• Input Range: 0 ~ 5.25 V
• Power (typ) @ Conditions: 8.5mW @ 500kSPS
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC081S051
• Lead Free Status / RoHS Status: Not applicable / Not applicable

7.2 Shutdown Mode
Shutdown mode is appropriate for applications that either do
not sample continuously, or it is acceptable to trade through-
put for power consumption. When the ADC is in shutdown
mode, all of the analog circuitry is turned off.
To enter shutdown mode, a conversion must be interrupted
by bringing CS high anytime between the second and tenth
To exit shutdown mode, bring CS back low. Upon bringing
CS low, the ADC will begin powering up (power-up time is
specified in the Timing Specifications table). This microsec-
ond of power-up delay results in the first conversion result
being unusable. The second conversion performed after pow-
er-up, however, is valid, as shown in
If CS is brought back high before the 10th falling edge of
SCLK, the device will return to shutdown mode. This is done
to avoid accidentally entering normal mode as a result of
noise on the CS line. To exit shutdown mode and remain in
normal mode, CS must be kept low until after the 10th falling
edge of SCLK. The ADC will be fully powered-up after 16
SCLK cycles.
8.0 POWER MANAGEMENT
The ADC takes time to power-up, either after first applying
V
This corresponds to one "dummy" conversion for any SCLK
frequency within the specifications in this document. After this
first dummy conversion, the ADC will perform conversions
properly. Note that the t
tween the first dummy conversion and the second valid con-
version.
When the V
in either of the two modes: normal or shutdown. As such, one
dummy conversion should be performed after start-up, as de-
scribed in the previous paragraph. The part may then be
placed into either normal mode or the shutdown mode, as
described in Sections 7.1 and 7.2.
When the ADC is operated continuously in normal mode, the
maximum guaranteed throughput is f
A
, or after returning to normal mode from shutdown mode.
A
supply is first applied, the ADC may power up
QUIET
time must still be included be-
SCLK
Figure
/ 20 at the maximum
9.
FIGURE 8. Entering Shutdown Mode
FIGURE 9. Entering Normal Mode
13
falling edges of SCLK, as shown in
been brought high in this manner, the device will enter shut-
down mode, the current conversion will be aborted and SDA-
TA will enter TRI-STATE. If CS is brought high before the
second falling edge of SCLK, the device will not change
mode; this is to avoid accidentally changing mode as a result
of noise on the CS line.
specified f
sumption by running f
performing fewer conversions per unit time, raising the ADC
CS line after the 10th and before the 15th fall of SCLK of each
conversion. A plot of typical power consumption versus
throughput is shown in the Typical Performance Curves sec-
tion. To calculate the power consumption for a given through-
put, multiply the fraction of time spent in the normal mode by
the normal mode power consumption and add the fraction of
time spent in shutdown mode multiplied by the shutdown
mode power consumption. Note that the curve of power con-
sumption vs. throughput is essentially linear. This is because
the power consumption in the shutdown mode is so small that
it can be ignored for all practical purposes.
9.0 POWER SUPPLY NOISE CONSIDERATIONS
The charging of any output load capacitance requires current
from the power supply, V
the supply to charge the output capacitance will cause voltage
variations on the supply. If these variations are large enough,
they could degrade SNR and SINAD performance of the ADC.
Furthermore, discharging the output capacitance when the
digital output goes from a logic high to a logic low will dump
current into the die substrate, which is resistive. Load dis-
charge currents will cause "ground bounce" noise in the sub-
strate that will degrade noise performance if that current is
large enough. The larger the output capacitance, the more
current flows through the die substrate and the greater is the
noise coupled into the analog channel, degrading noise per-
formance.
SCLK
. Throughput may be traded for power con-
SCLK
A
. The current pulses required from
at its maximum specified rate and
Figure
8. Once CS has
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