ADC14DS105LFEB/NOPB National Semiconductor, ADC14DS105LFEB/NOPB Datasheet
ADC14DS105LFEB/NOPB
Specifications of ADC14DS105LFEB/NOPB
Related parts for ADC14DS105LFEB/NOPB
ADC14DS105LFEB/NOPB Summary of contents
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... ADC14DS105's functionality. The ADC14DS105 is available in a 60-lead LLP package and operates over the industrial temperature range of −40°C to +85°C. Connection Diagram © 2007 National Semiconductor Corporation Features ■ Clock Duty Cycle Stabilizer ■ Single +3.0V or 3.3V supply operation ■ ...
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Block Diagram Ordering Information Industrial (−40°C www.national.com ≤ ≤ T +85°C) A ADC14DS105AISQ (offers higher SFDR) ADC14DS105CISQ ADC14DS105LFEB Evaluation Board for input frequency < 70MHz 2 20211202 Package 60 Pin LLP 60 Pin LLP ...
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Pin Descriptions and Equivalent Circuits Pin No. Symbol ANALOG I CMO 9 V ...
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Pin No. Symbol 57 PD_A 20 PD_B 27 TEST 47 WAM 48 DLC 45 OUTCLK+ 44 OUTCLK- 43 FRAME+ 42 FRAME- www.national.com Equivalent Circuit This is a two-state input controlling Power Down Power Down is enabled ...
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Pin No. Symbol Equivalent Circuit 38 SD1_A+ 37 SD1_A- 34 SD1_B+ 33 SD1_B- 36 SD0_A+ 35 SD0_A- 32 SD0_B+ 31 SD0_B- 56 SPI_EN 55 SCSb 52 SCLK 54 SDI Description Serial Data Output 1 for Channel A. This is a ...
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Pin No. Symbol 53 SDO 46 ORA 30 ORB 24 DLL_Lock ANALOG POWER 8, 16, 17, 58 12, 15, AGND Exposed Pad DIGITAL POWER 26, 40 25, 39, 51 DRGND www.national.com Equivalent ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage ( Voltage on Any Pin (Not to exceed 4.2V) Input Current at Any Pin other than Supply Pins (Note 4) Package Input Current (Note 4) ...
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Symbol Parameter Internal Reference Accuracy EXT External Reference Voltage V REF Dynamic Converter Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V +1.2V 105 MHz CLK CM CMO T ...
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Logic and Power Supply Electrical Characteristics Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V +1.2V 105 MHz CLK CM CMO . All other limits apply for T = ...
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Symb Parameter t SDI Hold Time H t SDO Driven-to-Tri-State Time ODZ t SDO Tri-State-to-Driven Time OZD t SDO Output Delay Time OD t SCSb Setup Time CSS t SCSb Hold Time CSH t Inter-Access Gap IAG LVDS Electrical Characteristics ...
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Note 9: With a full scale differential input of 2V P-P Note 10: Typical figures are 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not A guaranteed. Note ...
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Specification Definitions APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for conver- sion. APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample. ...
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Timing Diagrams FIGURE 2. Serial Output Data Format in Single-Lane Mode FIGURE 1. Serial Output Data Timing 13 20211214 20211217 www.national.com ...
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FIGURE 3. Serial Output Data Format in Dual-Lane Mode www.national.com 14 20211218 ...
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Transfer Characteristic FIGURE 4. Transfer Characteristic 15 20211210 www.national.com ...
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Typical Performance Characteristics DNL, INL specifications apply: AGND = DRGND = 0V, V DCS disabled 25°C. CM CMO A DNL www.national.com Unless otherwise specified, the following = +3.3V +3.0V, Internal V = ...
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Typical Performance Characteristics AGND = DRGND = 0V +3.3V MHz 25°C. CMO IN A SNR, SINAD, SFDR vs. V SNR, SINAD, SFDR vs. Clock Duty Cycle SNR, SINAD, ...
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Spectral Response @ 10 MHz Input Spectral Response @ 240 MHz Input www.national.com Spectral Response @ 70 MHz Input 20211268 IMD MHz 20211270 18 20211269 MHz IN 20211271 ...
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Functional Description Operating on a single +3.3V supply, the ADC14DS105 digi- tizes two differential analog input signals to 14 bits, using a differential pipelined architecture with error correction circuitry and an on-chip sample-and-hold circuit to ensure maximum performance. The user ...
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− REF CM V − REF − REF CM V ...
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Loading any of these pins, other than V may result in performance degradation. CMO The nominal voltages for the reference bypass pins are as follows 1.5 V CMO ...
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SCSb, SDI, SCLK These pins are part of the SPI interface. See Section 5.0 for more information. 4.0 DIGITAL OUTPUTS Digital outputs consist of six LVDS signal pairs (SD0_A, SD1_A, SD0_B, SD1_B, OUTCLK, FRAME) and CMOS logic outputs ORA, ...
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SCLK: Used to register the input data (SDI) on the rising edge; and to source the output data (SDO) on the falling edge. User may disable clock and hold it in the low-state, as long as clock pulse-width min spec ...
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Device Control Register, Address DLC DCS OF WAM PD_A PD_B Reset State : 08h Bits (7:6) Operational Mode 0 0 Normal Operation Test Output mode. A fixed test pattern (10100110001110 ...
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Reset State : 00h Bits (7:6) Reserved. Must be set to '0'. Bits (5:0) User Test Pattern. Most-significant 6 bits of the 14-bit pattern that will be sourced out of the data outputs in Test Output Mode. User Test Pattern ...
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Physical Dimensions TOP View...............................SIDE View...............................BOTTOM View www.national.com inches (millimeters) unless otherwise noted 60-Lead LLP Package Ordering Numbers: ADC14DS105AISQ / ADC14DS105CISQ NS Package Number SQA60A 26 ...
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Notes 27 www.national.com ...
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