SI3400-EVB Silicon Laboratories Inc, SI3400-EVB Datasheet - Page 6
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
SI3400-EVB
Manufacturer Part Number
SI3400-EVB
Description
BOARD EVAL FOR SI3400
Manufacturer
Silicon Laboratories Inc
Type
PWM Controllersr
Datasheet
1.SI3400-E1-GM.pdf
(20 pages)
Specifications of SI3400-EVB
Mfg Application Notes
SI3400/01 High Power AppNote Si3400/1 PoE PD Controllers AppNote
Main Purpose
Special Purpose DC/DC, Power Over Ethernet
Outputs And Type
1, Non-Isolated
Voltage - Output
5V
Voltage - Input
44 ~ 57V
Regulator Topology
Buck
Frequency - Switching
350kHz
Board Type
Fully Populated
Utilized Ic / Part
Si3400
Input Voltage
5 V
Output Voltage
3.3 V
Interface Type
Ethernet
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Product
Power Management Modules
For Use With/related Products
Si3400
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Current - Output
-
Power - Output
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1352
SI3400-EVB
SI3400-EVB
Si3400/Si3401
Table 4. Electrical Characteristics
6
VPORT
Input Offset Current
Diode bridge leakage
IPORT Classification
IPORT Operating Current
Current Limit
Hotswap FET On-Resistance +
R
Power loss VPORT Threshold
Switcher Frequency
Maximum Switcher Duty Cycle
Switching FET On-Resistance
Regulated Feedback @ pin FB
Regulated Output Voltage Tolerance
Notes:
SENSE
1. Transient surge defined in IEC60060 as a 1000 V impulse of either polarity applied to CT1–CT2 or SP1–SP2. The
2. The classification currents are guaranteed only when recommended RCLASS resistors are used, as specified in
3. IPORT includes full operating current of switching regulator controller.
4. The PD interface includes dual-level input current limit. At turn-on, before the HSO load capacitor is charged, the
5. See “AN296: Using the Si3400/01 PoE PD Controller in Isolated and Non-Isolated Designs” for more information.
6. Applies to non-isolated applications only (VOUT on schematic in Figure 1).
shape of the impulse shall have a 300 ns full rise time and a 50 µs half fall time with 201 Ω source impedance.
Table 10.
current limit is set at the inrush level. After the capacitor has been charged within ~1.25 V of VNEG, the operating
current limit is engaged. This higher current limit remains active until the UVLO lower limit has been tripped or until the
hotswap switch is sufficiently current-limited to cause a foldback of the HSO voltage.
4
Parameter
2
3
5
6
6
Output voltage tolerance @
ISOSSFT connected to
36 V < VPORT < 57 V
36 V < VPORT < 57 V
Transient Surge
UVLO Turn Off
UVLO Turn On
VPORT < 10 V
VPORT = 57 V
Classification
Description
Operating
Detection
DC Avg.
Class 0
Class 1
Class 2
Class 3
Class 4
Inrush
VOUT
VDD
Rev. 0.9
1
350 (Si3400)
470 (Si3401)
Min
2.7
0.5
0.3
62
27
–5
14
—
30
—
—
17
26
36
—
—
—
—
—
0
9
1.23
Typ
130
525
550
350
30
50
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
Max
0.86
3.1
1.4
11
22
42
36
79
10
25
12
20
30
44
33
—
—
—
—
—
4
5
Unit
kHz
mA
mA
µA
µA
mA
mA
%
%
Ω
Ω
V
V
V