LP3906SQ-JXXIEV National Semiconductor, LP3906SQ-JXXIEV Datasheet

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LP3906SQ-JXXIEV

Manufacturer Part Number
LP3906SQ-JXXIEV
Description
BOARD EVALUATION LP3906SQ-JXXI
Manufacturer
National Semiconductor
Series
PowerWise®r

Specifications of LP3906SQ-JXXIEV

Main Purpose
DC/DC, Step Down with LDO
Outputs And Type
4, Non-Isolated
Current - Output
1.5A, 1.5A, 300mA, 300mA
Regulator Topology
Buck
Frequency - Switching
2MHz
Board Type
Fully Populated
Utilized Ic / Part
LP3906
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Voltage - Output
-
Voltage - Input
-
Power - Output
-
Lead Free Status / Rohs Status
Supplier Unconfirmed
© 2010 National Semiconductor Corporation
Dual High-Current Step-Down DC/DC and Dual Linear
Regulator with I2C Compatible Interface
General Description
The LP3906 is a multi-function, programmable Power Man-
agement Unit, optimized for low power FPGAs, Microproces-
sors and DSPs. This device integrates two highly efficient
1.5A Step-Down DC/DC converters with dynamic voltage
management (DVM), two 300mA Linear Regulators and a
400kHz I
cess to the internal control registers of the LP3906. The
LP3906 additionally features programmable power-on se-
quencing and is offered in a tiny 5 x 4 x 0.8mm LLP-24 pin
package.
Key Specifications
Step-Down DC/DC Converter (Buck)
Linear Regulators (LDO)
1.5A output current
Programmable Vout from:
— Buck1 : 0.8V–2.0V
— Buck2 : 1.0V–3.5V
Up to 96% efficiency
2 MHz PWM switching frequency
±3% output voltage accuracy
Automatic soft start
Programmable V
±3% output voltage accuracy
300 mA output currents
25 mV (typ) Dropout
2
C compatible interface to allow a host controller ac-
OUT
of 1.0V–3.5V
201978
LP3906
Features
Applications
Compatible with advanced applications processors and
FPGAs
2 LDOs for powering Internal processor functions and I/Os
High speed serial interface for independent control of
device functions and settings
Precision internal reference
Thermal overload protection
Current overload protection
24-lead 5 × 4 × 0.8 mm LLP package
Software Programmable Regulators
FPGA, DSP core power
Applications processors
Peripheral I/O power
August 16, 2010
www.national.com

Related parts for LP3906SQ-JXXIEV

LP3906SQ-JXXIEV Summary of contents

Page 1

... Programmable V of 1.0V–3.5V OUT ■ ±3% output voltage accuracy ■ 300 mA output currents ■ (typ) Dropout © 2010 National Semiconductor Corporation LP3906 Features ■ Compatible with advanced applications processors and FPGAs ■ 2 LDOs for powering Internal processor functions and I/Os ■ ...

Page 2

Typical Application Circuit www.national.com FIGURE 1. Typical Application Circuit 2 20197801 ...

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For information about how schottky diodes can reduce noise in high load, high Vin applications, refer to "Buck Output Ripple Management" in the Application Notes section. FIGURE 2. Typical Application Circuit 3 20197863 www.national.com ...

Page 4

... Voltage VPFP LP3906SQ-VPFP Voltage VPFP LP3906SQX-VPFP Voltage PPXP LP3906SQ-PPXP Voltage PPXP LP3906SQX-PPXP Voltage FXPI LP3906SQ-FXPI Voltage FXPI LP3906SQX-FXPI Voltage KXII LP3906SQ-TKXII* Voltage KXII LP3906SQX-TKXII* * Note: Option only available with default EN_T of 001; all other options use 010. Default Voltage Options Version JXXI ...

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Pin Descriptions Pin Pin Name I/O 1 VIN2 2 SW2 O 3 GND_SW2 G 4 GND_C G 5 GND_SW1 G 6 SW1 O 7 VIN1 8 SDA I/O 9 SCL 10 EN_T 11 FB1 12 AVDD 13 VINLDO1 14 LDO1 ...

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... Absolute Maximum Ratings 2) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications SDA, SCL IN GND to GND SLUG Power Dissipation (P ) D_MAX (T =85°C, T =125° MAX (Note 5) Junction Temperature (T ) J-MAX Storage Temperature Range ...

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Low Drop Out Regulators, LDO1 and LDO2 Unless otherwise noted 3. 25°C. Limits appearing in boldface type apply over the entire junction temperature range for operation, −40°C to +125°C. 2, Note 7, Note 8, Note ...

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IO Electrical Characteristics Unless otherwise noted: Typical values and limits appearing in normal type apply for T type apply over the entire junction temperature range for operation, T Symbol Parameter V Input Low Level IL V Input High Level IH ...

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Typical Performance Characteristics — LDO Output Voltage Change vs Temperature (LDO1) Vin = 4.3V, Vout = 3.3V, 100 mA load Load Transient (LDO1) 3.6 Vin, 3.3 Vout, 0 – 100 mA load Line Transient (LDO1) 3.6 - 4.5 Vin, 3.3 ...

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Enable Start-up time (LDO1) ) 0-3.6 Vin, 3.3 Vout, 1mA load www.national.com Enable Start-up time (LDO2) 0 – 3.6 Vin, 1.8 Vout load 20197841 10 20197842 ...

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Typical Performance Characteristics T = 25°C unless otherwise noted A Shutdown Current vs. Temp Output Voltage vs. Supply Voltage (Vout = 1.8V) — Buck Output Voltage vs. Supply Voltage (Vout = 1.0 V) 20197843 Output Voltage vs. Supply Voltage 20197845 ...

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Buck 1 Efficiency vs Output Current (Forced PWM Mode, Vout =1.2V, L= 2.2µH) Buck 1 Efficiency vs Output Current (PFM to PWM mode, Vout =1.2V, L= 2.2µH) Buck 2 Efficiency vs Output Current (Forced PWM Mode, Vout =1.8V, L= 2.2µH) ...

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Buck 2 Efficiency vs Output Current (PFM to PWM Mode, Vout =1.8V, L= 2.2µH) Load Transient Response Vout = 1.2 (PWM Mode) 20197855 Line Transient Response Vin = 3 – 3.6 V, Vout = 1.2 V, 250 mA load 20197857 ...

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Start up into PWM Mode Vout = 1.8 V, 1.2 A load Start up into PFM Mode Vout = 1 load www.national.com Start up into PWM Mode Vout = 3.3 V, 1.2 A load 20197859 Start up ...

Page 15

DC/DC Converters OVERVIEW The LP3906 supplies the various power needs of the application by means of two Linear Low Drop Regulators LDO1 and LDO2 and two Buck converters SW1 and SW2. The table here under lists the output characteristics of ...

Page 16

SW1, SW2: Synchronous Step Down Magnetic DC/DC Converters FUNCTIONAL DESCRIPTION The LP3906 incorporates two high efficiency synchronous switching buck regulators, SW1 and SW2 that deliver a con- stant voltage from a single Li-Ion battery to the portable system processors. Using ...

Page 17

Quiescent supply current during this ‘sleep’ mode is less than 30 µA, which allows the part to achieve high efficiencies under extremely light load condi- tions. When the output drops below the ‘low’ PFM threshold, the ...

Page 18

POWER ON EN_T assertion causes the LP3906 to emerge from Standby mode to Full Operation mode at a preset timing sequence. By default, the enables for the LDOs and Bucks are internally pulled up, which causes the part to turn ...

Page 19

LP3906 Default Power-Up Sequence Power-On Timing Specification Symbol t Programmable Delay from EN_T assertion Programmable Delay from EN_T assertion Programmable Delay from EN_T assertion Programmable Delay from EN_T ...

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LP3906 Default Power-Off Sequence Symbol t Programmable Delay from EN_T deassertion Programmable Delay from EN_T deassertion Programmable Delay from EN_T deassertion Programmable Delay from EN_T deassertion to V ...

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Compatible Serial Interface SIGNALS The LP3906 features compatible serial interface, using two dedicated pins: SCL and SDA for I 2 spectively. Both signals need a pull-up resistor according to the ...

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LP3906 chip address : 0x60 When a READ function is to ...

Page 23

LP3906 Control Registers Register Register Read/ Address Name Write 0x02 ICRA R 0x07 SCR1 R/W 0x10 BKLDOEN R/W 0x11 BKLDOSR R 0x20 VCCR R/W 0x23 B1TV1 R/W 0x24 B1TV2 R/W 0x25 B1RC R/W 0x29 B2TV1 R/W 0x2A B2TV2 R/W 0x2B ...

Page 24

INTERRUPT STATUS REGISTER (ISRA) 0X02 This register informs the user of the temperature status of the chip. D7-2 D1 — Name Temp 125°C — Access R Data Reserved Status bit for thermal warning PMIC T>125°C Reset 0 0 CONTROL 1 ...

Page 25

BUCK AND LDO OUTPUT VOLTAGE ENABLE REGISTER (BKLDOEN) – 0X10 This register controls the enables for the Bucks and LDOs — Name LDO2EN — Access R/W Data Reserved 0 – Disable 1 – Enable Reset 0 1 BUCK ...

Page 26

BUCK1 TARGET VOLTAGE 1 REGISTER (B1TV1) – 0X23 This register allows the user to program the output target volt- age of Buck 1. D7-5 — Name — Access Data Reserved Buck1 Output Voltage (V) 5’h00 5’h01 5’h02 5’h03 5’h04 5’h05 ...

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BUCK 1 RAMP CONTROL REGISTER (B1RC) - 0x25 This register allows the user to program the rate of change between the target voltages of Buck 1. D7 Name - - - - Access - - - - Data Reserved Reset ...

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BUCK 2 TARGET VOLTAGE 1 REGISTER (B2TV1) – 0X29 This register allows the user to program the output target volt- age of Buck 2. D7-5 — Name — Access Data Reserved Buck2 Output Voltage (V) 5’h00 5’h01 5’h02 5’h03 5’h04 ...

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BUCK 2 RAMP CONTROL REGISTER (B2RC) - 0x2B This register allows the user to program the rate of change between the target voltages of Buck 2 D7 Name - - - - Access - - - - Data Reserved Reset ...

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BUCK FUNCTION REGISTER (BFCR) – 0x38 This register allows the Buck switcher clock frequency to be spread across a wider range, allowing for less Electro-magnetic Interference (EMI). The spread spectrum modulation frequency refers to the rate at which the frequency ...

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LDO1 CONTROL REGISTER (LDO1VCR) – 0X39 This register allows the user to program the output target volt- age of LDO 1. D7-5 — Name LDO1_OUT — Access Data Reserved LDO1 Output voltage (V) 5’h00 5’h01 5’h02 5’h03 5’h04 5’h05 5’h06 ...

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Application Notes SYSTEM CLOCK INPUT (SYNC) PIN Pin 23 of the chip allows for a system clock input in order to synchronize the buck converters in PWM mode. This is useful if the user wishes to force the bucks to ...

Page 33

For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure correct device operation. The capacitor value can change greatly, depend- ing on the operating conditions and capacitor type. In particular, the output capacitor selection ...

Page 34

Note that the output voltage ripple is dependent on the induc- tor current ripple and the equivalent series resistance of the output capacitor (R ). The R is frequency dependent as ESR ESR well as temperature dependent. The R lated ...

Page 35

MODE BOUNCE PFM-PWM transition at low load current. To improve efficiency at lower load currents LP3906 buck converters employ an automatically invoked PFM mode for the low load operation. The PFM mode operates with a much lower value quiescent current ...

Page 36

High Vin-High Load Operation Additional information is provided when the IC is operated at extremes of Vin and regulator loads. These are described in terms of the Junction temperature and, Buck output ripple management. Junction Temperature The maximum junction temperature ...

Page 37

Thermal Performance of the LLP Package The LP3906 is a monolithic device with integrated power FETs. For that reason important to pay special attention to the thermal impedance of the LLP package and to the PCB layout rules ...

Page 38

Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 0.8 mm 24-Pin LLP Package 38 ...

Page 39

Notes 39 www.national.com ...

Page 40

... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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