LP3906SQ-JXXIEV National Semiconductor, LP3906SQ-JXXIEV Datasheet - Page 17

• Manufacturer Part Number: LP3906SQ-JXXIEV
• Description: BOARD EVALUATION LP3906SQ-JXXI
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LP3906SQ-JXXIEV

• Main Purpose: DC/DC, Step Down with LDO
• Outputs And Type: 4, Non-Isolated
• Current - Output: 1.5A, 1.5A, 300mA, 300mA
• Regulator Topology: Buck
• Frequency - Switching: 2MHz
• Board Type: Fully Populated
• Utilized Ic / Part: LP3906
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Voltage - Output: -
• Voltage - Input: -
• Power - Output: -
• Lead Free Status / Rohs Status: Supplier Unconfirmed

tremely low power mode. Quiescent supply current during this
‘sleep’ mode is less than 30 µA, which allows the part to
achieve high efficiencies under extremely light load condi-
tions. When the output drops below the ‘low’ PFM threshold,
the cycle repeats to restore the output voltage to ~1.6% above
the nominal PWM output voltage.
If the load current should increase during PFM mode (see
figure below) causing the output voltage to fall below the
‘low2’ PFM threshold, the part will automatically transition into
fixed-frequency PWM mode.
SW1, SW2 OPERATION
SW1 and SW2 have selectable output voltages ranging from
0.8V to 3.5V (typ.). Both SW1 and SW2 in the LP3906 are
I
SHUTDOWN MODE
During shutdown the PFET switch, reference, control and
bias circuitry of the converters are turned off. The NFET
switch will be on in shutdown to discharge the output. When
the converter is enabled, soft start is activated. It is recom-
mended to disable the converter during the system power up
and under voltage conditions when the supply is less than
2.8V.
SOFT START
The soft-start feature allows the power converter to gradually
reach the initial steady state operating point, thus reducing
start-up stresses and surges. The two LP3906 buck convert-
ers have a soft-start circuit that limits in-rush current during
start-up. During start-up the switch current limit is increased
in steps. Soft start is activated only if EN goes from logic low
to logic high after VIN reaches 2.8V. Soft start is implemented
by increasing switch current limit in steps of 213 mA, 425 mA,
850 mA and 1700 mA (typ. Switch current limit). The start-up
time thereby depends on the output capacitor and load cur-
rent demanded at start-up.
LOW DROPOUT OPERATION
The LP3906 can operate at 100% duty cycle (noswitching;
PMOS switch completely on) for low drop out support of the
output voltage. In this way the output voltage will be controlled
2
C register controlled and are enabled by default through the
17
internal state machine of the LP3906 following a Power-On
event that moves the operating mode to the Active state. (see
Power On Sequence). The SW1 and SW2 output voltages
revert to default values when the power on sequence has
been completed. The default output voltage for each buck
converter is factory programmable. (See Application Notes).
SW1, SW2 can be enabled/disabled through the correspond-
ing control register.
The Modulation mode PWM/PFM is by default automatic and
depends on the load as described above in the functional de-
scription. The modulation mode can be overridden by setting
I
forcing the buck to operate in PWM mode regardless of the
load condition.
down to the lowest possible input voltage. When the device
operates near 100% duty cycle, output voltage ripple is ap-
proximately 25 mV. The minimum input voltage needed to
support the output voltage is
V
FLEXIBLE POWER SEQUENCING OF MULTIPLE POWER
SUPPLIES
The LP3906 provides several options for power on sequenc-
ing. The two bucks can be individually controlled with ENSW1
and ENSW2. The two LDOs can also be individually con-
trolled with ENLDO1 and ENLDO2.
If the user desires a set power on sequence, all four enables
should be tied LOW so that the regulators don’t automatically
enable when power is supplied. The user can then program
the chip through I
activate the power on sequencing.
— I
— R
— R
2
C bit to a logic 1 in the corresponding buck control register,
IN, MIN
LOAD
DSON, PFET
INDUCTOR
= I
LOAD
* (R
2
C and raise EN_T from LOW to HIGH to
Load current
Drain to source resistance of
Inductor resistance
DSON, PFET
PFET switch in the triode region
+ R
INDUCTOR
) + V
20197803
OUT
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