LM5035EVAL National Semiconductor, LM5035EVAL Datasheet - Page 15

• Manufacturer Part Number: LM5035EVAL
• Description: BOARD EVALUATION LM5035
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of LM5035EVAL

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Isolated
• Voltage - Output: 3.3V
• Current - Output: 30A
• Voltage - Input: 36 ~ 75V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5035
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Power - Output: -

sistor (R
is a fixed voltage (2.5V). An example will illustrate the use of
the Volt • Second Clamp comparator to achieve a 50% duty
cycle limit at 200kHz with a 48V line input. A 50% duty cycle
at a 200kHz requires a 2.5µs on-time. To achieve this maxi-
mum on-time clamp level:
The recommended capacitor value range for C
1000pF. 470pF is a standard value that can be paired with an
110kΩ to approximate the desired 51.4µs time constant. If
load transient response is slowed by the 10% margin, the
R
be slightly decreased by increasing R
Oscillator, Sync Capability
The LM5035 oscillator frequency is set by a single external
resistor connected between the RT and AGND pins. To set a
desired oscillator frequency, the necessary RT resistor is cal-
culated from:
For example, if the desired oscillator frequency is 400kHz (HO
and LO each switching at 200kHz) a 15kΩ resistor would be
the nearest standard one percent value.
Each output (HO, LO, SR1 and SR2) switches at half the os-
cillator frequency. The voltage at the RT pin is internally
regulated to a nominal 2V. The RT resistor should be located
as close as possible to the IC, and connected directly to the
pins (RT and AGND). The tolerance of the external resistor,
and the frequency tolerance indicated in the Electrical Char-
acteristics, must be taken into account when determining the
worst case frequency range.
The LM5035 can be synchronized to an external clock by ap-
plying a narrow pulse to the RT pin. The external clock must
be at least 10% higher than the free-running oscillator fre-
quency set by the RT resistor. If the external clock frequency
is less than the RT resistor programmed frequency, the
LM5035 will ignore the synchronizing pulses. The synchro-
nization pulse width at the RT pin must be a minimum of 15
ns wide. The clock signal should be coupled into the RT pin
through a 100pF capacitor or a value small enough to ensure
the pulse width at RT is less than 60% of the clock period
under all conditions. When the synchronizing pulse transi-
FF
value can be increased. The system signal-to-noise will
FF
) connected to VIN while the threshold of the clamp
FF
x C
FF
.
FF
is 100pF to
15
tions low-to-high (rising edge), the voltage at the RT pin must
be driven to exceed 3.2V volts from its nominal 2 VDC level.
During the clock signal’s low time, the voltage at the RT pin
will be clamped at 2 VDC by an internal regulator. The output
impedance of the RT regulator is approximately 100Ω. The
RT resistor is always required, whether the oscillator is free
running or externally synchronized.
Gate Driver Outputs (HO & LO)
The LM5035 provides two alternating gate driver outputs, the
floating high side gate driver HO and the ground referenced
low side driver LO. Each driver is capable of sourcing 1.25A
and sinking 2A peak. The HO and LO outputs operate in an
alternating manner, at one-half the internal oscillator frequen-
cy. The LO driver is powered directly by the VCC regulator.
The HO gate driver is powered from a bootstrap capacitor
connected between HB and HS. An external diode connected
between VCC (anode pin) and HB (cathode pin) provides the
high side gate driver power by charging the bootstrap capac-
itor from VCC when the switch node (HS pin) is low. When
the high side MOSFET is turned on, HB rises to a peak volt-
age equal to V
The HB and VCC capacitors should be placed close to the
pins of the LM5035 to minimize voltage transients due to par-
asitic inductances since the peak current sourced to the MOS-
FET gates can exceed 1.25A. The recommended value of the
HB capacitor is 0.01µF or greater. A low ESR / ESL capacitor,
such as a surface mount ceramic, should be used to prevent
voltage droop during the HO transitions.
The maximum duty cycle for each output is limited to slightly
less than 50% due to the internally fixed deadtime and any
programmed sync rectifier delay. The typical deadtime in this
condition is 70 ns. The programmed sync rectifier delay is
determined by the DLY pin resistor. If the COMP pin is open
circuit, the outputs will operate at maximum duty cycle. The
maximum duty cycle for each output can be calculated with
the following equation:
Where T
HO or LO outputs, TD is the internally fixed deadtime, and T1
is the programmed sync rectifier delay. For example, if the
oscillator frequency is 200 kHz, each output will cycle at 100
kHz (T
no programmed delay, the maximum duty cycle at this fre-
quency is calculated to be 49.3%. Using a programmed sync
rectifier delay of 100 ns, the maximum duty cycle is reduced
to 48.3%.
S
= 10 µs). Using the nominal deadtime of 70 ns and
S
is the period of one complete cycle for either the
VCC
+ V
HS
where V
HS
is the switch node voltage.
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