DP83848C-POE-EK National Semiconductor, DP83848C-POE-EK Datasheet - Page 2

• Manufacturer Part Number: DP83848C-POE-EK
• Description: BOARD EVALUATION DP83848C
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DP83848C-POE-EK

• Main Purpose: Special Purpose DC/DC, Power Over Ethernet
• Outputs And Type: 1, Isolated
• Power - Output: 24W
• Voltage - Output: 3.3V
• Current - Output: 7.3A
• Voltage - Input: 39 ~ 57V
• Regulator Topology: Flyback
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: LM5072
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

www.national.com
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Usage setup and Configuration
This section contains information about the setup and con-
figuration of the POEPHYTEREV-I/-E evaluation board, in-
cluding descriptions of the card's interfaces, connectors,
jumpers and LEDs.
Power for the POEPHYTEREV board can be supplied by a
number of means:
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Additional information for all options above may be found in the DP83848 datasheet.
Status indicators: LEDs
The POEPHYTEREV board supplies numerous status indi-
cators via LEDs.
Status provided include:
Link - DS3*
Media Speed - DS2
Activity/Collision - DS4*
Ethernet Device Power - DS1
PoE Power - LED1
System interface will be via the MII connector, and MII
header
RJ-45 for network connection
JTAG access via 2x5 header
MII connector J1
PoE over unused pairs
PoE over data pairs
External supply to P1
If 5V is supplied from the MII connector, the on-board
voltage regulator, U2, will convert 5V to 3.3V for the
PHYTER®. J7 should be removed.
J10 (Not populated)
J11 (Not populated)
J6(Not populated)
Jumper
J12
J1
J2
J3
J4
J5
J7
J8
J9
MII Male Connector
PWR_DWN/INT
MII 3V3 option
MII Header
Pulse Jack
LED_CFG
RESET_N
MDIX_EN
PHYAD1
Name
Table of Jumpers
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Address Settings:
The PMD address for the DP83848 Physical Layer device is
set by jumper J3.
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*Other status can be indicated by these LEDs. The alternate
status is set by adding jumper J5. Refer the DP83848
datasheet for additional information.
Ethernet Performance
The DP83848 PHYTER® supports line speed Ethernet net-
work communications. Signal quality, which affects IEEE
compliance, can vary depending on board layout, power sup-
plies, and components used, esp. isolation magnetics.
Function
MII interface
Alternative connection for MII signals
PHY Address strap pin
Enable/Disable MDIX mode. (Default is Auto-MDIX Enable)
Set LED configuration. See datasheet
Use 3V3 MII supply
Set Power Down and Interrupt Mode. See datasheet
Reset the device
Integrated Magnetic RJ-45 connector
If 3.3V is supplied from the MII connector, J7 needs to be
ON (See schematics for details).
Only applies to the circuit board version with PCB serial
number 551013040-001 Rev A: J7 should be shorted if the
PoE main output is set at 3.3V, which is the default factory
setting. To modify the output to other higher voltages, a
3.3V LDO should be installed onto U2 and J7 must be
open.
Default board setting for the PHY Address is 01h
The board may be set to PHY Address 03h by adding
jumper J3