EL7536EVAL1 Intersil, EL7536EVAL1 Datasheet - Page 8

• Manufacturer Part Number: EL7536EVAL1
• Description: EVALUATION BOARD FOR EL7536
• Manufacturer: Intersil

Specifications of EL7536EVAL1

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.8V
• Current - Output: 1A
• Voltage - Input: 2.5 ~ 5.5V
• Regulator Topology: Buck
• Board Type: Fully Populated
• Utilized Ic / Part: EL7536
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Power - Output: -
• Frequency - Switching: -

At extreme conditions (V
temperature higher than 75°C), input cap C
recommended to be 22µF. Otherwise, if any of the above 3
conditions is not true, C
The RMS current present at the input capacitor is decided by
the following formula:
This is about half of the output current I
input capacitor must be able to handle this current.
The inductor peak-to-peak ripple current is given as:
• L is the inductance
• f
The inductor must be able to handle I
current, and to assure that the inductor is reliable, it must
handle the 1.5A surge current that can occur during a
current limit condition.
In addition to decoupling capacitors and inductor value, it is
important to properly size the phase-lead capacitor C
(Refer to the Typical Application Diagram). The phase-lead
capacitor creates additional phase margin in the control loop
by generating a zero and a pole in the transfer function. As a
general rule of thumb, C
lead at a frequency of ~2.5kHz. The zero will always appear
at lower frequency than the pole and follow the equation
below:
Over a normal range of R
~470-4700pF. The pole frequency cannot be set once the
zero frequency is chosen as it is dictated by the ratio of R
and R
point. The equation below shows the pole frequency
relationship:
Current Limit and Short-Circuit Protection
The current limit is set at about 1.5A for the PMOS. When a
short-circuit occurs in the load, the preset current limit
restricts the amount of current available to the output, which
causes the output voltage to drop below the preset voltage.
In the meantime, the excessive current heats up the
regulator until it reaches the thermal shut-down point.
ΔI
f
f
Z
P
I
INRMS
IL
S
=
=
=
the switching frequency (nominally 1.4MHz)
----------------------
2πR
---------------------------------------
2π R
2
(
------------------------------------------- -
, which is solely determined by the desired output set
V
(
1
IN
=
L
2
1
C
×
----------------------------------------------- -
1
- V
4
V
R
V
IN
O
2
O
)C
×
×
)
×
(
V
4
f
V
S
V
IN
IN
O
- V
1
4
IN
O
can remain as low as 10µF.
2
should be sized to start the phase-
)
(~10-100k), C
< 3V, I
×
I
8
O
O
> 0.7A, and junction
O
O
for the RMS load
4
for all the V
will range from
1
is
O
4
. This
1
EL7536
Thermal Shut-Down
Once the junction reaches about 145°C, the regulator shuts
down. Both the P channel and the N channel MOSFETs turn
off. The output voltage will drop to zero. With the output
MOSFETs turned off, the regulator will soon cool down.
Once the junction temperature drops to about 130°C, the
regulator will restart again in the same manner as EN pin
connects to logic HI.
Thermal Performance
The EL7536 is in a fused-lead MSOP10 package. Compared
with regular MSOP10 package, the fused-lead package
provides lower thermal resistance. The θ
4-layer board and 125°C/W on 2-layer board. Maximizing the
copper area around the pins will further improve the thermal
performance.
Layout Considerations
The layout is very important for the converter to function
properly. The following PC layout guidelines should be
followed:
• Separate the Power Ground ( ) and Signal Ground (
• Place the input capacitor as close to V
• Make the following PC traces as small as possible:
• If used, connect the trace from the FB pin to R1 and R2 as
• Maximize the copper area around the PGND pin
• Place several via holes under the chip to additional ground
The demo board is a good example of layout based on this
outline. Please refer to the EL7536 Application Brief.
connect them only at one point right at the pins
as possible
- from L
- from C
close as possible
plane to improve heat dissipation
X
O
pin to L
to PGND
JA
IN
and PGND pins
is 100°C/W on a
July 13, 2006
FN7396.8
);