ISL6310EVAL1Z Intersil, ISL6310EVAL1Z Datasheet - Page 5

• Manufacturer Part Number: ISL6310EVAL1Z
• Description: EVALUATION BOARD FOR ISL6310
• Manufacturer: Intersil

Specifications of ISL6310EVAL1Z

• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 1.5V
• Current - Output: 60A
• Voltage - Input: 5 ~ 12V
• Regulator Topology: Buck
• Frequency - Switching: 400kHz
• Board Type: Fully Populated
• Utilized Ic / Part: ISL6310
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power - Output: -

0A
ISL6310 Performance
Soft-Start Interval
The typical start-up waveforms for the ISL6310EVAL1Z are
shown in Figure 5. The waveforms represented in this image
show the soft-start sequence of the regulator DAC set to
1.50V. Before the soft-start interval begins, VCC and PVCC
are above POR and the DAC is set to 11. With these two
conditions met, throwing the ENABLE switch into the OFF
position causes the voltage on the ENLL pin to rise above
the ISL6310’s enable threshold, beginning the soft-start
sequence. For a delay time of 0.6ms, V
due to the manner in which soft-start is implemented within
the controller. After this delay (which is approximately equal
to 240 switching cycles), V
toward the DAC voltage. With the converter running at
400kHz, this ramp takes approximately 4.3ms, during which
time the input current, ICC12, also ramps slowly due to the
controlled building of the output voltage.
Once V
down on the PGOOD pin is released. This allows a resistor
from PGOOD to VCC to pull PGOOD high and the PGOOD
LED indicator changes from red to green.
Special consideration is given to start-up into a pre-charged
output (where the output is not 0V at the time the SS cycle is
initiated). Under such circumstances, the ISL6310 keeps off
both sets of output MOSFETs until the internal ramp starts to
exceed the output voltage sensed at the FB pin. This special
scenario is detailed in Figure 6. The circuit is enabled at time
T0. As the internal ramp exceeds the magnitude of the output
voltage at time T1, the MOSFETs drivers are enabled and the
output voltage ramps up in a seamless fashion from the pre-
existent level to the DAC-set level, reached at time T2.
0A
0V
0V
FIGURE 5. SOFT-START INTERVAL WAVEFORMS
OUT
reaches the DAC set point, the internal pull-
OUT
1ms/DIV
5
begins to ramp linearly
OUT
ICC12
ENLL
V
ICORE,
OUT
does not move
Application Note 1197
GND>
GND>
A second scenario can be encountered with a pre-charged
output: output being pre-charged above the DAC-set point,
as shown in Figure 7. In this situation, the ISL6310 behaves
in a way similar to that of Figure 6, keeping the MOSFETs off
until the end of the SS ramp. However, once the end of the
ramp has been reached, at time T1, the output drivers are
enabled for operation, and the output is quickly drained
down to set-point level.
GND>
An OV condition during start-up will take precedence over
this normal start-up behavior, but will allow reversal back to
normal behavior as soon as the condition is removed or
brought under control.
GND>
GND>
GND>
GND>
GND>
FIGURE 7. ISL6310EVAL1Z START-UP INTO AN
FIGURE 6. ISL6310EVAL1Z START-UP INTO A PARTIALLY
PHASE1
PHASE1
PHASE2
PHASE1
ENLL
T0
OVERCHARGED OUTPUT (V
PHASE2
CHARGED OUTPUT (V
PHASE2
T0
V
OUT
ENLL
ENLL
VOUT
V
OUT
1ms/DIV
1ms/DIV
1ms/DIV
T1
T1
T2
DAC
DAC
= 1.200V)
= 1.200V)
December 12, 2006
AN1197.1