ISL6559EVAL2 Intersil, ISL6559EVAL2 Datasheet - Page 6

• Manufacturer Part Number: ISL6559EVAL2
• Description: EVALUATION BOARD 2 ISL6559
• Manufacturer: Intersil

Specifications of ISL6559EVAL2

• Main Purpose: Special Purpose DC/DC, VRM Supply
• Outputs And Type: 1, Non-Isolated
• Power - Output: 67.6W
• Voltage - Output: 1.3V
• Current - Output: 52A
• Voltage - Input: 5V, 12V
• Regulator Topology: Buck
• Frequency - Switching: 250kHz
• Board Type: Fully Populated
• Utilized Ic / Part: HIP6601, ISL6559
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

and/or load sharing. The scale factor is set by the ratio of the
ISEN resistors and the lower MOSFET r
desired, connect this pin to FB. When not used for droop or
load sharing, simply leave this pin open.
VSEN, RGND, VDIFF
VSEN and RGND are the inputs to the differential remote-
sense amplifier. Connect these pins to the sense points of
the remote load. Connect an appropriately sized feedback
resistor, R
VCC
Supplies all the power necessary to operate the chip. The IC
starts to operate when the voltage on this pin exceeds the
rising POR threshold and shuts down when the voltage on
this pin drops below the falling POR threshold. Connect this
pin directly to a +5V supply or through a series 300Ω resistor
to a +12V supply.
ISEN1, ISEN2, ISEN3, ISEN4
Current sense inputs. A resistor connected between these
pins and their respective phase node sets a current
proportional to the current in the lower MOSFET during it’s
conduction interval. This current is used as a reference for
channel balancing, load sharing, protection, and load-line
regulation. Inactive channels should have their respective
sense inputs left open.
PWM1, PWM2, PWM3, PWM4
Pulse-width modulating outputs. Connect these pins to the
individual HIP660x driver PWM input pins. These logic
outputs command the driver IC(s) in switching the half-
bridge configuration of MOSFETs.The number of active
channels is determined by the state of PWM3 and PWM4. If
PWM3 is tied to VCC, this indicates to the controller that two
channel operation is desired. In this case, PWM 4 should be
left open or tied to VCC. Shorting PWM4 to VCC indicates
that three channel operation is desired.
PGOOD
Power good is an open-drain logic output that changes to a
logic low when the voltage at VDIFF is 350mV below the VID
setting or above 2.2V.
FS/DIS
A dual function pin for setting the switching frequency and
disabling the controller. Place a resistor from this pin to
ground to set the switching frequency between 80kHz and
1MHz. Pulling this pin below 0.8V disables the controller.
EN
Threshold sensitive enable input of the controller. Transition
this pin above 1.23V (typical enable threshold) to initiate a
soft-start cycle. Pull this pin below 1.14V, taking into account
the enable hysteresis, to disable the controller once in
operation. Connect a resistor divider to this pin to set the
power-on voltage level for proper coordination with Intersil
FB
, between VDIFF and FB.
6
DS(ON)
. If droop is
ISL6559
MOSFET drivers. If this function is not required, simply tie
this pin to VCC.
Multi-Phase Power Conversion
Microprocessor load current profiles have changed to the
point where the multi-phase power conversion advantage is
pronounced. The technical challenges associated with
producing a single-phase converter which is both cost-
effective and thermally viable have forced a change to the
cost-saving approach of multi-phase. The ISL6559 controller
helps reduce the complexity of implementation by integrating
vital functions and requiring minimal output components.
The block diagram in Figure 1 provides a top level view of
multi-phase power conversion using the ISL6559 controller.
Interleaving
The switching of each channel in a multi-phase converter is
timed to be symmetrically out of phase with each of the other
channels. In a 3-phase converter, each channel switches 1/3
cycle after the previous channel and 1/3 cycle before the
following channel. As a result, the three-phase converter has
a combined ripple frequency three times greater than the
ripple frequency of any one phase. In addition, the peak-to-
peak amplitude of the combined inductor currents is reduced
in proportion to the number of phases (Equations 1 and 2).
Increased ripple frequency and lower ripple amplitude mean
that the designer can use less per-channel inductance and
lower total output capacitance for any performance
specification.
Figure 1 illustrates the multiplicative effect on output ripple
frequency. The three channel currents (IL1, IL2, and IL3),
combine to form the AC ripple current and the DC load
current. The ripple component has three times the ripple
frequency of each individual channel current. Each PWM
pulse is terminated 1/3 of a cycle, or 1.33µs, after the PWM
pulse of the previous phase. The peak-to-peak current
waveforms for each phase is about 7A, and the dc
components of the inductor currents combine to feed the load.
FIGURE 1. PWM AND INDUCTOR-CURRENT WAVEFORMS
PWM1, 5V/DIV
IL1 + IL2 + IL3, 7A/DIV
FOR 3-PHASE CONVERTER
IL1, 7A/DIV
PWM3, 5V/DIV
1µs/DIV
IL3, 7A/DIV
PWM2, 5V/DIV
IL2, 7A/DIV
December 29, 2004
FN9084.8