NCP1582DR2GEVB ON Semiconductor, NCP1582DR2GEVB Datasheet - Page 6

• Manufacturer Part Number: NCP1582DR2GEVB
• Description: EVAL BOARD FOR NCP1582DR2G
• Manufacturer: ON Semiconductor

Specifications of NCP1582DR2GEVB

• Design Resources: NCP1582 EVB BOM NCP1582 EVB Schematic NCP1582DR2GEVB Gerber Files
• Main Purpose: DC/DC, Step Down
• Outputs And Type: 1, Non-Isolated
• Voltage - Output: 0.8V
• Voltage - Input: 4.5 ~ 12 V
• Regulator Topology: Buck
• Frequency - Switching: 350kHz
• Board Type: Fully Populated
• Utilized Ic / Part: NCP1582
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Output: -
• Power - Output: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: NCP1582DR2G
• Other names: NCP1582DR2GEVBOS

General
DC−DC conversion from 5.0 V & 12 V buses. The NCP158x
has a 0.7 A internal gate driver circuit designed to drive
N−channel MOSFETs in a synchronous−rectifier buck
topology. The output voltage of the converter can be
precisely regulated down to 800 mV 1.5% when the V
is tied to V
high gain operational transconductance error amplifier
(OTA) is used.
Duty Cycle and Maximum Pulse Width Limits
at an operating point defined by the ratio of the input to the
output voltage. The NCP158x can achieve an 80% duty
cycle. There is a built in off−time which ensures that the
bootstrap supply is charged every cycle. The NCP158x,
which is capable of a 100 nsec pulse width (min.), can allow
a 12 V to 0.8 V conversion at 350 kHz.
Input Voltage Range (V
13.2 V with respect to GND and PHASE, respectively.
Although BST is rated at 13.2 V with respect to PHASE, it
can also tolerate 26.5 V with respect to GND.
External Enable/Disable
below the 400 mv threshold, it disables the PWM Logic and
the gate drive outputs. In this disabled mode, the operational
transconductance error amplifier’s (EOTA) output source
current is reduced and limited to the Soft Start current of 10 mA.
Normal Shutdown Behavior
because the input supply reaches UVLO threshold. In this
case, switching stops, the internal SS is discharged, and all
GATE pins go low. The switch node enters a high impedance
state and the output capacitors discharge through the load
with no ringing on the output voltage.
External Soft Start
which reduces inrush current and overshoot of the output
voltage. Soft start is achieved by using the internal current
source of 10 mA. (typ), which charges the external integrator
capacitor of the transconductance amplifier. Figure 10 is a
typical soft start sequence. This sequence begins once V
surpasses its UVLO threshold. During Soft Start, as the
Comp Pin rises through 400 mV, the PWM Logic and gate
drives are enabled. When the feedback voltage crosses
800 mV, the EOTA will be given control to switch to its
higher regulation mode output current of 120 mA. In the
event of an overcurrent during soft start, the overcurrent
logic will override the soft start sequence and will shut down
the PWM logic and both the high side and low side gates.
The NCP158x is an 8−pin PWM controller intended for
In steady state DC operation, the duty cycle will stabilize
The input voltage range for both V
When the Comp pin voltage falls or is pulled externally
Normal shutdown occurs when the IC stops switching
The NCP158x features an external soft start function,
OUT
. The switching frequency is internally set. A
CC
and BST)
CC
DETAILED OPERATING DESCRIPTION
and BST is 4.5 V to
http://onsemi.com
FB
pin
CC
6
UVLO
unexpected behavior does not occur when V
support the internal rails and power the converter. For the
NCP158x, the UVLO is set to ensure that the IC will start up
when V
below 3.7 V. This permits operation when converting from
a 5.0 input voltage.
Current Limit Protection
FET will conduct large currents. The controller will shut
down the regulator in this situation for protection against
overcurrent. The low−side R
comparing the voltage at the Phase node when BG starts
going low to an internally generated fixed voltage. If the
phase voltage is lower than SCP trip voltage, an overcurrent
condition occurs and a counter is initiated. When the counter
completes, the PWM logic and both HS−FET and LS−FET
are turned off. The controller will retry to see if the short
circuit or overload condition is removed through the soft
start cycle. The minimum turn−on time of the LS−FET is set
to be 500 ns. The trip thresholds have a −95 mV, +45 mV
process and temperature variation.
Drivers
external N−channel MOSFETs. This allows the NCP158x to
address high−power as well as low−power conversion
requirements. The gate drivers also include adaptive
non−overlap circuitry. The non−overlap circuitry increase
efficiency, which minimizes power dissipation, by
minimizing the body diode conduction time.
drive circuitry used in the chip is shown in Figure 11.
Isource/
Enable
Under Voltage Lockout (UVLO) is provided to ensure that
In case of a short circuit or overload, the low−side (LS)
The NCP158x includes 0.7 A gate drivers to switch
A detailed block diagram of the non−overlap and gate
V
Sink
comp
V
fb
CC
-10 mA
10 mA
Figure 10. Soft Start Implementation
reaches 4.2 V and shutdown when V
Timing Diagram NCP1582: Enable Sequence
Start Up
0.4 V
1.1 V
SS
DSon
Normal
120 mA
sense is implemented by
10 mA
CC
0.4 V
is too low to
CC
drops