CDB4352 Cirrus Logic Inc, CDB4352 Datasheet - Page 11

• Manufacturer Part Number: CDB4352
• Description: BOARD EVAL FOR CS4352 DAC
• Manufacturer: Cirrus Logic Inc
• Series: Popguard®r

Specifications of CDB4352

• Number Of Dac's: 2
• Number Of Bits: 24
• Outputs And Type: 2, Single Ended
• Sampling Rate (per Second): 192k
• Data Interface: Serial
• Dac Type: Voltage
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: CS4352
• Description/function: Audio D/A
• Operating Supply Voltage: 3.3 V
• Product: Audio Modules
• For Use With/related Products: CS4352
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Contains lead / RoHS non-compliant
• Other names: 598-1518

DS684F2
4. APPLICATIONS
4.1
4.2
Sample Rate Range/Operational Mode Detect
The device operates in one of three operational modes. The allowed sample rate range in each mode is
auto-detected.
The CS4352 will auto-detect the correct mode when the input sample rate (Fs), defined by the LRCK fre-
quency, falls within one of the ranges illustrated in
each mode are not supported.
System Clocking
The device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK) clocks.
The left/right clock, defined also as the input sample rate (F
MCLK according to specified ratios. The specified ratios of MCLK to LRCK, along with several standard au-
dio sample rates and the required MCLK frequency, are illustrated in
Refer to
to
Sample Rate
“Switching Specifications - Serial Audio Interface” on page 8
Sample Rate
(kHz)
88.2
96
(kHz)
Section 4.3
44.1
32
48
Input Sample Rate (F
Sample Rate
170 kHz - 216 kHz
84 kHz - 108 kHz
4 kHz - 54 kHz
for the required SCLK timing associated with the selected Digital Interface Format and
(kHz)
176.4
11.2896
12.2880
192
128x
Table 3. Double-Speed Mode Standard Frequencies
Table 2. Single-Speed Mode Standard Frequencies
Table 4. Quad-Speed Mode Standard Frequencies
11.2896
12.2880
8.1920
256x
Table 1. CS4352 Auto-Detect
S
)
22.5792
24.5760
16.9344
18.4320
128x
192x
12.2880
16.9344
18.4320
384x
Table
MCLK (MHz)
MCLK (MHz)
33.8688
36.8640
MCLK (MHz)
192x
1. Sample rates outside the specified range for
22.5792
24.5760
16.3840
22.5792
24.5760
256x
512x
s
), must be synchronously derived from the
for the maximum allowed clock frequencies.
Tables
Double-Speed Mode
Single-Speed Mode
Quad-Speed Mode
45.1584
49.1520
256x
33.8688
36.8640
24.5760
33.8688
36.8640
Mode
2-4.
384x
768x
45.1584
49.1520
32.7680
45.1584
49.1520
1024x
CS4352
512x
11