EVAL-AD5372EBZ Analog Devices Inc, EVAL-AD5372EBZ Datasheet
EVAL-AD5372EBZ
Specifications of EVAL-AD5372EBZ
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EVAL-AD5372EBZ Summary of contents
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FEATURES 32-channel DAC in a 64-lead LQFP AD5372/AD5373 1 guaranteed monotonic to 16/14 bits Maximum output voltage span of 4 × VREF (20 V) Nominal output voltage range of − Multiple, independent output voltage spans available ...
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AD5372/AD5373 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 General Description ......................................................................... 3 Specifications..................................................................................... 4 AC Characteristics........................................................................ 5 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 9 ESD Caution.................................................................................. 9 Pin Configuration ...
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GENERAL DESCRIPTION The AD5372/AD5373 contain 32 16-/14-bit DACs in a single 64-lead LQFP. The devices provide buffered voltage outputs with a nominal span of 4× the reference voltage. The gain and offset of each DAC can be independently trimmed to ...
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AD5372/AD5373 SPECIFICATIONS open circuit open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications ...
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Parameter POWER REQUIREMENTS Power Supply Sensitivity ∆Full Scale/∆V DD ∆Full Scale/∆V SS ∆Full Scale/∆ Power-Down Mode Power Dissipation (Unloaded) 3 ...
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AD5372/AD5373 TIMING CHARACTERISTICS open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T L Table ...
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SCLK SYNC DB23 SDI BUSY 1 LDAC 1 VOUTx 2 LDAC 2 VOUTx CLR VOUTx t 19 RESET VOUTx BUSY 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY. ...
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AD5372/AD5373 SCLK SYNC SDI DB23 SDO DB0 DB23 INPUT WORD SPECIFIES REGISTER TO BE READ DB0 DB23 SELECTED REGISTER DATA CLOCKED OUT LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timing OUTPUT VOLTAGE 8V ACTUAL TRANSFER ...
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ABSOLUTE MAXIMUM RATINGS T = 25°C, unless otherwise noted. Transient currents not cause SCR latch-up. Table 5. Parameter V to AGND AGND DGND CC Digital Inputs to ...
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AD5372/AD5373 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET BUSY VOUT27 SIGGND3 VOUT28 VOUT29 VOUT30 VOUT31 CONNECT Table 6. Pin Function Descriptions Pin No. Mnemonic Description 1 RESET Digital Reset ...
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TYPICAL PERFORMANCE CHARACTERISTICS –1 –2 0 16384 32768 DAC CODE Figure 8. Typical AD5372 INL Plot 1.0 0.5 0 –0.5 –1 TEMPERATURE (°C) Figure 9. Typical INL Error vs. Temperature 25°C ...
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AD5372/AD5373 0. –12V +12V DD VREFx = +3V 0. +5.5V CC 0.40 0. +2.5V CC 0.30 0.25 –40 – TEMPERATURE (°C) Figure 14. DI vs. Temperature CC 13.5 I ...
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TERMINOLOGY Integral Nonlinearity (INL) Integral nonlinearity, or endpoint linearity measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function measured after adjusting for zero-scale error and full-scale error ...
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AD5372/AD5373 THEORY OF OPERATION DAC ARCHITECTURE The AD5372/AD5373 contain 32 DAC channels and 32 output amplifiers in a single package. The architecture of a single DAC channel consists of a 16-bit (AD5372) or 14-bit (AD5373) resistor-string DAC followed by an ...
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A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT Each DAC channel has seven data registers. The actual DAC data-word can be written to either the X1A or the X1B input register, depending on the setting of the A /B bit in the control ...
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AD5372/AD5373 OUTPUT AMPLIFIER Because the output amplifiers can swing to 1.4 V below the positive supply and 1.4 V above the negative supply, this limits how much the output can be offset for a given reference voltage. For example, it ...
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The required reference levels can be calculated as follows: 1. Identify the nominal output range on VOUT. 2. Identify the maximum offset span and the maximum gain required on the full output signal range. 3. Calculate the new maximum output ...
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AD5372/AD5373 ADDITIONAL CALIBRATION The techniques described in the previous section are usually enough to reduce the zero-scale and full-scale errors in most applications. However, there are limitations whereby the errors may not be sufficiently reduced. For example, the offset (C) ...
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POWER-DOWN MODE The AD5372/AD5373 can be powered down by setting Bit 0 in the control register to 1. This turns off the DACs, thus reducing the current consumption. The DAC outputs are connected to their respective SIGGNDx potentials. The power-down ...
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AD5372/AD5373 SERIAL INTERFACE The AD5372/AD5373 contain a high speed SPI operating at clock frequencies MHz (20 MHz for read operations). To minimize both the power consumption of the device and on-chip digital noise, the interface powers up ...
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CHANNEL ADDRESSING AND SPECIAL MODES If the mode bits are not 00, the data-word D15 to D0 (AD5372) or D13 to D0 (AD5373) is written to the device. Address Bit A5 to Address Bit A0 determine which channels are written ...
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AD5372/AD5373 SPECIAL FUNCTION MODE If the mode bits are 00, then the special function mode is selected, as shown in Table 15. Bit I21 to Bit I16 of the serial data-word select the special function, and the remaining bits are ...
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APPLICATIONS INFORMATION POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consider- ation of the power supply and ground return layout helps to ensure the rated performance. The printed circuit boards on which the AD5372/AD5373 are mounted should ...
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... AD5372BSTZ-REEL −40°C to +85°C 1 AD5373BSTZ −40°C to +85°C 1 AD5373BSTZ-REEL −40°C to +85°C 1 EVAL-AD5372EBZ 1 EVAL-AD5373EBZ RoHS Compliant Part. ©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. 0.75 0.60 1.60 MAX 0 ...