CDB-43L21 Cirrus Logic Inc, CDB-43L21 Datasheet
CDB-43L21
Specifications of CDB-43L21
CDB-43L21
Related parts for CDB-43L21
CDB-43L21 Summary of contents
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Low Power, Stereo Digital to Analog Converter FEATURES 98 dB Dynamic Range (A-wtd) -86 dB THD+N Headphone Amplifier - GND Centered – On-Chip Charge Pump Provides -VA_HP – No DC-Blocking Capacitor Required 46 mW Power Into Stereo 16 Ω @ ...
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APPLICATIONS Portable Audio Players MD Players PDAs Personal Media Players Portable Game Consoles Smart Phones Wireless Headsets 2 GENERAL DESCRIPTION The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modulation, it allows ...
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TABLE OF CONTENTS 1. PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE .................................................................. 6 1.1 Digital I/O Pin Characteristics ........................................................................................................... 8 2. TYPICAL CONNECTION DIAGRAMS ................................................................................................... 9 3. CHARACTERISTIC AND SPECIFICATION TABLES ......................................................................... 11 SPECIFIED OPERATING CONDITIONS ............................................................................................. 11 ABSOLUTE MAXIMUM RATINGS ...
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Power Control 1 (Address 02h) ...................................................................................................... 39 6.3 Speed Control (Address 03h) ......................................................................................................... 40 6.4 Interface Control (Address 04h) ..................................................................................................... 41 6.5 DAC Output Control (Address 08h) ................................................................................................ 41 6.6 DAC Control (Address 09h) ............................................................................................................ 42 6.7 PCMX Mixer ...
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LIST OF FIGURES Figure 1.Typical Connection Diagram (Software Mode) ............................................................................. 9 Figure 2.Typical Connection Diagram (Hardware Mode) .......................................................................... 10 Figure 3.Headphone Output Test Load ..................................................................................................... 15 Figure 4.Serial Audio Interface Slave Mode Timing .................................................................................. 17 Figure 5.Serial Audio Interface Master ...
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PIN DESCRIPTIONS - SOFTWARE (HARDWARE) MODE LRCK SDA/CDIN (MCLKDIV2) SCL/CCLK (I²S/LJ) ADO/CS (DEM) VA_HP FLYP GND_HP FLYN Pin Name # Left Right Clock (Input/Output) - Determines which channel, Left or Right, is currently active on the 1 LRCK serial ...
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AOUTB Analog Audio Output (Output) - The full-scale output level is specified in the DAC Analog Characteris- 11 AOUTA tics specification table 12 VA Analog Power (Input) - Positive power for the internal analog section. 13 AGND Analog Ground ...
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Digital I/O Pin Characteristics The logic level for each input should not exceed the maximum ratings for the VL power supply. Pin Name I/O SW/(HW) RESET Input SCL/CCLK Input (I²S/LJ) SDA/CDIN Input/Output (MCLKDIV2) AD0/CS Input (DEM) MCLK Input LRCK ...
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TYPICAL CONNECTION DIAGRAMS +1 +2 µF 0.1 µ 1.5 µF 1 µF See Note 1.5 µF 1 µF * *Use low ESR ceramic capacitors. Note 4 : Larger capacitors, such ...
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FLYP ** 1 µF FLYN VSS_HP ** 1 µF GND_HP * *Use low ESR ceramic capacitors. MCLK SCLK LRCK SDIN VL or DGND See Note 3 47 kΩ Digital Audio TSTO/M/S Processor RESET ...
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CHARACTERISTIC AND SPECIFICATION TABLES (All Min/Max characteristics and specifications are guaranteed over the Specified Operating Conditions. Typical per- formance characteristics and specifications are derived from measurements taken at nominal supply voltages and T = 25° C.) A SPECIFIED OPERATING ...
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ANALOG OUTPUT CHARACTERISTICS (COMMERCIAL - CNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth kHz; Sample Frequency = 48 kHz; test load Ω, ...
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ANALOG OUTPUT CHARACTERISTICS (AUTOMOTIVE - DNZ) (Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement bandwidth kHz; Sample Frequency = 48 kHz and 96 kHz; test load R ...
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LINE OUTPUT VOLTAGE CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band- width kHz; Sample Frequency = 48 kHz; test load R Parameter Ω AOUTx Voltage ...
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HEADPHONE OUTPUT POWER CHARACTERISTICS Test conditions (unless otherwise specified): Input test signal is a full-scale 997 Hz sine wave; measurement band- width kHz; Sample Frequency = 48 kHz; test load R Parameter Ω AOUTx Power ...
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COMBINED DAC INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE Parameter Frequency Response kHz Passband StopBand StopBand Attenuation (Note 9) Group Delay De-emphasis Error Notes: 8. Response is clock dependent and will scale with Fs. Note that the ...
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LRCK SCLK SDIN Figure 4. Serial Audio Interface Slave Mode Timing Parameters Master Mode (Note 12) Output Sample Rate (LRCK) LRCK Duty Cycle SCLK Frequency SCLK Duty Cycle LRCK Edge to SDIN MSB Rising Edge SDIN Setup Time Before SCLK ...
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SWITCHING SPECIFICATIONS - I²C (Inputs: Logic 0 = DGND, Logic 1 = VL, SDA C Parameter SCL Clock Frequency RESET Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock pulse) Clock Low ...
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SWITCHING CHARACTERISTICS - SPI (Inputs: Logic 0 = DGND, Logic 1 = VL) Parameter CCLK Clock Frequency RESET Rising Edge to CS Falling CS Falling to CCLK Edge CS High Time Between Transmissions CCLK Low Time CCLK High Time CDIN ...
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DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to ground.) Parameters VQ Characteristics Nominal Voltage Output Impedance DC Current Source/Sink (Note 16) FILT+ VSS_HP Characteristics Nominal Voltage DC Current Source Power Supply Rejection Ratio (PSRR) 16. The ...
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POWER CONSUMPTION See (Note 19) Operation 1 Off (Note 20) 2 Standby (Note 21) 5 Mono Playback 6 Stereo Playback 19. Unless otherwise noted, test conditions are as follows: All zeros input, slave mode, sample rate = 48 kHz; No ...
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APPLICATIONS 4.1 Overview 4.1.1 Architecture The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling ratio of 128Fs. The D/A operates ...
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Hardware Mode A limited feature-set is available when the D/A powers up in Hardware Mode (see Up Sequence” section on page of functions/features, the default configuration and the associated stand-alone control available. Hardware Mode Feature/Function Summary Feature/Function Power Control ...
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Analog Outputs AOUTA and AOUTB are the ground-centered line or headphone outputs. Various signal processing options are available, including an internal Beep Generator. The desired path to the DAC must be selected using the DATA_SEL[1:0] bits. Software “DAC Control ...
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Gain -10dB 4.3.2 Volume Controls Two digital volume control functions offer independent control of the SDIN signal path into the mixer as well as a combined control of the mixed signals. The volume controls are programmable to ramp in incre- ...
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CONTINUOUS BEEP: Beep turns configurable frequency (FREQ) and volume (BPVOL) and remains REPEAT = '1' on until REPEAT is cleared. BEEP = '1' MULTI-BEEP: Beep turns configurable frequency (FREQ) REPEAT = '1' and volume ...
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Input MAX[2:0] Limiter Volume Output (after Limiter) MAX[2:0] 4.3.7 Line-Level Outputs and Filtering The CODEC contains on-chip buffer amplifiers capable of producing line level single-ended outputs on AOUTA and AOUTB. These amplifiers are ground centered and do not have any ...
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On-Chip Charge Pump An on-chip charge pump derives a negative supply voltage from the VA_HP supply. This provides dual rail supplies allowing a full-scale output swing centered around ground and eliminates the need for large, DC-blocking capacitors. Added benefits ...
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Slave LRCK and SCLK are inputs in Slave Mode. The speed of the D/A is automatically determined based on the input MCLK/LRCK ratio when the Auto-Detect function is enabled. Certain input clock ratios will then require an internal divide-by-two ...
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High-Impedance Digital Output The serial port may be placed on a clock/data bus that allows multiple masters for the SCLK/LRCK I/O without the need for external buffers. The 3ST_SP bit places the internal buffers for these I ...
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LRCK L eft SCLK SDIN AOUTA / AINxA LRCK L eft SCLK SDIN AOUTA 4.6 Initialization The initialization and Power-Down sequence ...
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Recommended Power-Down Sequence To minimize audible pops when turning off or placing the D/A in standby, 1. Mute the DAC’s. 2. Set the PDN bit in the power control register to ‘1’b. The D/A will not power down until ...
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Software Mode The control port is used to access the registers allowing the D configured for the desired operational modes and formats. The operation of the control port may be completely asynchronous with respect to the audio ...
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MAP allows successive reads or writes of consecutive registers. Each byte is separated by an acknowledge bit. The ACK bit is output from the from the microcontroller after each transmitted byte. CS43L21 ...
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Memory Address Pointer (MAP) The MAP byte comes after the address byte and selects the register to be read or written. Refer to the pseudo code above for implementation details. 4.9.3.1 Map Increment (INCR) The device has MAP auto-increment ...
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REGISTER QUICK REFERENCE Software mode register defaults are as shown. “Reserved” registers must maintain their default state. Addr Function 7 01h ID Chip_ID4 Chip_ID3 default 02h Power Ctl. 1 Reserved PDN_DACB PDN_DACA default ...
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Addr Function 7 0Fh Reserved Reserved Reserved 1 default 10h Vol. Control MUTE_PCM PCMMIXA PCMMIXA MIXA default 11h Vol. Control MUTE_PCM PCMMIXB PCMMIXB MIXB default 12h BEEP Freq. & FREQ3 OnTime ...
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Addr Function 7 0 default 1Dh Reserved Reserved Reserved 0 default 1Eh Reserved Reserved Reserved 0 default 1Fh Reserved Reserved Reserved 0 default 20h Status Reserved SP_CLKER default 21h CHRG_ CHRG_ FREQ3 default 38 ...
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REGISTER DESCRIPTION All registers are read/write except for the chip I.D. and Revision Register and Interrupt Status Register which are read only. See the following bit definition tables for bit assignment information. The default state of each bit after ...
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Power Down (PDN) Default Disable 1 - Enable Function: The entire D/A will enter a low-power state when this function is enabled. The contents of the control port registers are retained in this mode. 6.3 Speed Control ...
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Function: Divides the input MCLK by 2 prior to all internal circuitry. This bit is ignored when the AUTO bit is disabled in Slave Mode. 6.4 Interface Control (Address 04h Reserved M/S DAC_DIF2 Master/Slave Mode (M/S) Default: 0 ...
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Function: These bits select the gain multiplier for the headphone/line outputs. See tics” on page 14 and “Headphone Output Power Characteristics” on page DAC Single Volume Control (DAC_SNGVOL) Default: 0 Function: The individual channel volume levels are independently controlled by ...
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Freeze Controls (FREEZE) Default: 0 Function: This function will freeze the previous settings of, and allow modifications to be made to all control port reg- isters without the changes taking effect until the FREEZE is disabled. To have multiple changes ...
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Soft Ramp Soft Ramp allows level changes, either by gain changes, attenuation changes or muting implemented by incrementally ramping, in 1/8 dB steps, from the current level to the new level at a rate of 0.5 dB per ...
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Beep Frequency & Timing Configuration (Address 12h FREQ3 FREQ2 FREQ1 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Beep Frequency (FREQ[3:0]) Default: 0000 FREQ[3:0] Frequency Fs = ...
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Beep Off Time & Volume (Address 13h OFFTIME2 OFFTIME1 OFFTIME0 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Beep Off Time (OFFTIME[2:0]) Default: 000 OFFTIME[2:0] Off Time ...
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Beep Configuration & Tone Configuration (Address 14h REPEAT BEEP Reserved Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Repeat Beep (REPEAT) Default Disabled 1 ...
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Tone Control Enable (TC_EN) Default = Disabled 1 - Enabled Function: The Bass and Treble tone control features are active when this bit is enabled. 6.11 Tone Control (Address 15h TREB3 TREB2 TREB1 Note: The ...
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AOUTx Volume Control: AOUTA (Address 16h) & AOUTB (Address 17h AOUTx_VOL7 AOUTx_VOL6 AOUTx_VOL5 AOUTx_VOL4 AOUTx_VOL3 AOUTx_VOL2 AOUTx_VOL1 AOUTx_VOL0 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. AOUTX ...
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Limiter Threshold SZC Disable (Address 19h MAX2 MAX1 MAX0 Note: The DATA_SEL[1:0] bits in reg09h must be set to ‘01’b to enable function control in this register. Maximum Threshold (MAX[2:0]) Default: 000 MAX[2:0] Threshold Setting (dB) 000 ...
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Limiter Soft Ramp Disable (LIM_SRDIS) Default Off Function: Overrides the DAC_SZC setting. When this bit is set, the Limiter attack and release rate will not be dictated by the soft ramp setting. Note: This ...
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Limiter RELEASE Rate (RRATE[5:0]) Default: 111111 Binary Code 000000 ··· 111111 Function: Sets the rate at which the limiter releases the digital attenuation from levels below the minimum setting in the limiter threshold register, and returns the analog output level ...
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Signal Processing Engine Overflow (SPEX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path after the signal processing engine. PCMX Overflow (PCMX_OVFL) Default: 0 Function: Indicates a digital overflow condition within the data path of the PCM ...
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... ANALOG PERFORMANCE PLOTS 7.1 Headphone THD+N versus Output Power Plots Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; measurement band- width kHz kHz. Plots were taken from the CDB43L21 using an Audio Precision an- alyzer. -10 -15 VA_HP = VA = 1.8 V -20 ...
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VA_HP = VA = 1.8 -20 -30 -35 -40 -45 - -65 -70 -75 -80 -85 -90 -95 -100 0 6m 12m 18m 24m Figure 23. THD+N vs. Output Power per Channel at 1.8 ...
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Headphone Amplifier Efficiency The architecture of the headphone amplifier is that of typical class AB amplifiers. Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback w/16 Ω ...
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EXAMPLE SYSTEM CLOCK FREQUENCIES 8.1 Auto Detect Enabled Sample Rate LRCK (kHz) 8 11.025 12 Sample Rate LRCK (kHz) 16 22.05 24 Sample Rate LRCK (kHz) 32 44.1 48 Sample Rate LRCK (kHz) 64 88.2 96 *The”MCLKDIV2” pin 4 ...
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Auto Detect Disabled Sample Rate LRCK (kHz) 512x 8 - 11.025 - 12 6.1440 Sample Rate LRCK (kHz) 256x 16 - 22. 6.1440 Sample Rate LRCK (kHz) 32 44.1 48 Sample Rate LRCK (kHz) 64 88.2 96 ...
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PCB LAYOUT CONSIDERATIONS 9.1 Power Supply, Grounding As with any high-resolution converter, the CS43L21 requires careful attention to power supply and ground- ing arrangements if its potential performance realized. power arrangements, with VA and VA_HP connected ...
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FILTERS Figure 27. Passband Ripple Figure 29. Transition Band 60 CS43L21 Figure 28. Stopband Figure 30. Transition Band (Detail) DS723A1 ...
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DEFINITIONS Dynamic Range The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth. Dynamic Range is a signal-to-noise ratio measurement over the specified band width made with ...
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DIMENSIONS 32L QFN ( BODY) PACKAGE DRAWING D Pin #1 Corner Top View INCHES DIM MIN 0.0000 b 0.0071 0.0091 D 0.1969 BSC D2 0.1280 0.1299 E 0.1969 BSC E2 0.1280 0.1299 e ...
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... I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS723A1 Package Pb-Free Grade Temp Range Commercial -10 to +70° C 32L-QFN Yes Automotive -40 to +85° Changes CS43L21 Container Order # Rail CS43L21-CNZ Tape & Reel CS43L21-CNZR Rail CS43L21-DNZ Tape & Reel CS43L21-DNZR - - CDB43L21 63 ...