HI5731-EVS Intersil, HI5731-EVS Datasheet
HI5731-EVS
Specifications of HI5731-EVS
Related parts for HI5731-EVS
HI5731-EVS Summary of contents
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... TM Application Note Introduction The HI5731 bit 100MHz Digital to Analog Converter. This current out DAC is designed for low glitch and high Spurious Free Dynamic Range operation result, this DAC is ideally suited for Signal Reconstruction and DDS (Direct Digital Synthesis) applications due to its inherent low noise design ...
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... The HI5731 has a maximum clock rate specification of 100MHz. The data setup time before the 50% point of the I9 rising edge of the clock 0.5ns (Min). Logic levels are 0.8V (Max) for an input low H and 2.0V (Min) for a logic high. The HI5731 is both TTL and I7 CMOS input compatible D11 - D0 I4 CLK ...
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... For a D/A Converter, the differential non-linearity is the worst case deviation from the ideal step size throughout the entire code range. For the HI5731, this worst case deviation is said most 1.0 LSB in magnitude. For any given D/A converter, to guarantee no missing codes the converter must be monotonic. The defi ...
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... reconstructed sine wave out of the HI5731 is not ideal and as such has harmonics of the fundamental. The difference between the magnitude of the fundamental and the highest noise spur whether it is harmonically related to the fundamental or not, is the definition of Spurious Free Dynamic Range. Figures 10, through 15 are sample plots taken of the HI5731 at various frequencies ...
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Application Note 9602 FIGURE 10A. OSCILLOSCOPE PLOT FIGURE 10. A 1MHz FUNDAMENTAL -10 -20 -30 -40 -50 -60 -70 -80 -90 500kHz FIGURE 11. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED FIGURE 12A. OSCILLOSCOPE PLOT FIGURE ...
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Application Note 9602 FIGURE 13A. OSCILLOSCOPE PLOT FIGURE 13. A 5MHz FUNDAMENTAL -10 -20 -30 -40 -50 -60 -70 -80 -90 4MHz FIGURE 14. A 5MHz FUNDAMENTAL ON A 2MHz SPAN UNFILTERED FIGURE 15A. OSCILLOSCOPE PLOT FIGURE ...
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... NCOM EVALUATION BOARD CLOCK CIRCUIT SOFTWARE INCLUDED PERSONAL COMPUTER FIGURE 16. INTERSIL HI5731/DDS EVALUATION SYSTEM SETUP BLOCK DIAGRAM 3-7 Application Note 9602 Center Frequency This 32-bit hexadecimal word will create the fundamental. In order to ensure zero phase offset the cursor should be moved to the LOAD select. Pressing the spacebar the value should be toggled from and back to 1 again ...
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... GND 312 C 313 0.1 F 0.01 F GND GND GND GND FIGURE 17. NOTES: 1. All passive components are SMT devices, except polarized capacitors and ferrite beads. 2. HI5731 lead DIP or SOIC. SMA 976 21 IOUT 20 IOUTB 24 R COMPIN COMPOUT 26 REFOUT 23 RSET GND 19 ARET 27 AVSS 22 AVEE GND ...
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... Application Note 9602 FIGURE 17A. HI5731 SILKSCREEN FIGURE 17C. HI5731 LAYER 2 3-9 FIGURE 17B. HI5731 LAYER 1 FIGURE 17D. HI5731 LAYER 3 ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see web site http://www.intersil.com 3-10 Application Note 9602 FIGURE 18E. HI5731 LAYER 4 ...