HI5741-EVS Intersil, HI5741-EVS Datasheet

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HI5741-EVS

Manufacturer Part Number
HI5741-EVS
Description
EVALUATION PLATFORM HI5741
Manufacturer
Intersil
Datasheets

Specifications of HI5741-EVS

Number Of Dac's
1
Number Of Bits
14
Outputs And Type
1, Differential
Sampling Rate (per Second)
100M
Data Interface
Parallel
Settling Time
20ns
Dac Type
Current
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
HI5741
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Introduction
The HI5741 is a 14-bit 100MHz Digital to Analog Converter.
This current out DAC is designed for low glitch and high
Spurious Free Dynamic Range operation. As a result, this
DAC is ideally suited for Signal Reconstruction and DDS
(Direct Digital Synthesis) applications due to its inherent low
noise design.
Architecture
The HI5741 DAC is designed with a split architecture to
minimize glitch while maximizing linearity. Figure 1 shows
the functional architecture of the device. The 10 least
significant bits of the converter are derived by a traditional
R/2R network to binarily weight the 1.28mA (nominal)
current sources. The upper 4, or most significant bits, are
implemented as segmented or thermometer decoded
current sources. The thermometer decoder converts the
(MSB) D13
(LSB) D0
CLK
D10
D11
D12
D1
D2
D3
D4
D5
D6
D7
D8
D9
AV
EE
AGND
REGISTER
MASTER
14-BIT
TM
3-1
DV
EE
1-888-INTERSIL or 321-724-7143
DGND
Application Note
BUFFER/
SHIFTER
LEVEL
DATA
V
CC
FIGURE 1. HI5741 BLOCK DIAGRAM
OVERDRIVEABLE
REFERENCE
DECODER
VOLTAGE
UPPER
4-BIT
Using The HI5741 Evaluation Module
|
Intersil and Design is a trademark of Intersil Corporation.
incoming 4 bits to 15 control lines to enable the most
significant current sources.
As shown in Figure 2, the thermometer decoder translates
the 4 bit binary input data into a decode that enables
individual current sources. For example, a binary code of
0110 on the data bits D10 through D13 will enable current
sources I1, I2, I3, I4, I5, and I6. The thermometer decoding
architecture ensures good differential non-linearity, which is
further enhanced by the addition of laser trimming. Also,
compared to a straight R/2R design, the worst case glitch is
greatly reduced since creating the MSB current is the sum of
current sources I1 through I8. Overall glitch is therefore
reduced by a factor of 16. This also reduces the theoretical
switching skew from current source to current source by
using identically sized switches with identical gain, leakage,
and transient responses.
REGISTER
SLAVE
REF OUT
July 1996
SWITCHED
CURRENT
CURRENT
REF CELL
10 LSBs
R
CELLS
CELLS
SET
15
+
-
NETWORK
|
Copyright
R/2R
25
©
Intersil Corporation 2000
I
CTRL AMP
I
IN
CTRL AMP
OUT
OUT
OUT
AN9626

Related parts for HI5741-EVS

HI5741-EVS Summary of contents

Page 1

... TM Application Note Introduction The HI5741 is a 14-bit 100MHz Digital to Analog Converter. This current out DAC is designed for low glitch and high Spurious Free Dynamic Range operation result, this DAC is ideally suited for Signal Reconstruction and DDS (Direct Digital Synthesis) applications due to its inherent low noise design ...

Page 2

... In traditional DACs the worst case glitch usually occurs at the major transition i.e., 01 1111 1111 1111 to 10 0000 0000 0000. But in the HI5741 the worst case glitch is moved to the 00 0011 1111 1111 to 11 1100 000 0000 transition. This is achieved by the split R/2R segmented current source architecture ...

Page 3

... The worst case integral linearity of the HI5741 is specifi less than 1.5 LSB. The implementation of laser trim assures 14-bit match from current cell to current cell. Figure 5 graphically illustrates the typical linearity performance of the HI5741. 1.5 1.0 0.5 0 -0.5 -1.0 -1.5 0 5000 ...

Page 4

... Application Note AN9619 “Optimizing Setup Conditions for High Accuracy Measurements of the HI5741” for further details on the use of filtering for evaluation purposes. A reconstructed sine wave out of the HI5741 is not ideal and as such has harmonics of the fundamental. The difference between the magnitude of the fundamental and the highest ...

Page 5

... Spurious Free Dynamic Range. Figures 10 through 15 are sample plots taken of the HI5741 at various frequencies. In all the cases Typical Performance Curves ~ CH1 200mV M 100ns FIGURE 10A. OSCILLOSCOPE PLOT FIGURE 10. A 1MHz FUNDAMENTAL TO -100 CENTER 1 ...

Page 6

Typical Performance Curves CH1 200mV M 50.0ns FIGURE 12A. OSCILLOSCOPE PLOT FIGURE 12. A 5MHz FUNDAMENTAL TO ~ CH1 200mV M 100ns FIGURE 13A. OSCILLOSCOPE PLOT FIGURE 13. A 1MHZ FUNDAMENTAL TO 3-6 Application Note 9626 (Continued) 0 -10 -20 ...

Page 7

Typical Performance Curves -100 FIGURE 14. A 1MHz FUNDAMENTAL ON A 1MHz SPAN UNFILTERED ~ CH1 200mV M 50.0ns FIGURE 15A. OSCILLOSCOPE PLOT FIGURE 15. A 5MHz FUNDAMENTAL TO Using the HSP-EVAL Test Platform The HSP-EVAL DDS platform allows quick ...

Page 8

... Application Note 9626 Figures 17 and 18 graphically illustrate two examples of test patterns used to evaluate MTPR performance on the HI5741. In figure 17, a ten tone pattern is used with tones ranging from 2MHz to 3MHz with 100kHz tone spacing. Figure 18 illustrates a similar pattern, however 40kHz tone spacing is used. In both cases, the fifth tone has been removed to observe the third order harmonic products and the amount of distortion they introduce into the spectrum ...

Page 9

Test Patterns CH1 200mV M 2.00 s FIGURE 17A. SCOPE PLOT OF MTPR TEST WAVEFORM CH1 200mV M 200 s FIGURE 17C. SCOPE PLOT OF MTPR TEST WAVEFORM 3-9 Application Note 9626 0 -10 -20 -30 -40 -50 -60 -70 ...

Page 10

... IOUT 20 IOUTB 24 R COMPIN COMPOUT 26 REFOUT 23 R 976 3 RSET GND 19 ARET GND HI5741 0 10.0 F 0.1 F 0.01 F GND GND GND NOTE: Place as close to device pin 22 as possible 0.1 F 0.01 F GND GND NOTE: Place as close to device pin 18 as possible. SMA J ...

Page 11

Application Note 9626 FIGURE 19A. SILKSCREEN FIGURE 19B. LAYER 1 FIGURE 19C. LAYER 2 3-11 ...

Page 12

Application Note 9626 FIGURE 19D. LAYER 3 FIGURE 19E. LAYER 4 FIGURE 19F. SILKSCREEN 3-12 ...

Page 13

... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...

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