MAX5661EVCMAXQU+ Maxim Integrated Products, MAX5661EVCMAXQU+ Datasheet - Page 19

• Manufacturer Part Number: MAX5661EVCMAXQU+
• Description: EVALUATION SYSTEM FOR MAX56611
• Manufacturer: Maxim Integrated Products

Specifications of MAX5661EVCMAXQU+

• Number Of Dac's: 1
• Number Of Bits: 16
• Outputs And Type: 2, Single Ended
• Data Interface: Serial
• Dac Type: Current/Voltage
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: MAX5661
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX5661 single 16-bit DAC with precision high-volt-
age amplifiers provides a complete solution for program-
mable current and voltage-output applications. The
programmable output amplifiers swing to industry-stan-
dard voltage levels of ±10V or current levels from 0mA
(or from 4mA) to 20mA. The OUTV voltage output drives
resistive loads greater than 2kΩ and capacitive loads up
to 1.2µF. Force and sense connections on the voltage
output compensate for series protection resistors and
field wiring resistance. Short-circuit protection on the
voltage output limits output current. The OUTI current
output drives resistive loads from 0Ω and higher, up to a
compliance voltage of (V
output also drives inductive loads up to 1H.
The MAX5661 provides a current output or a voltage
output, with only one output active at any given time.
The MAX5661 operates with ±13.48V to ±15.75V dual
supplies (V
+13.48V to +40V single supply (V
output (see Table 16). The +4.75V to +5.25V digital sup-
ply (V
ers the rest of the internal analog circuitry. A buffered
reference input accepts a +4.096V reference voltage.
The LDAC and CLR inputs asynchronously update the
DAC outputs. CLR sets the DAC code to the value
stored in the clear register (software clear), or to zero
scale (hardware clear). The FAULT output asserts for
an open-circuit current output, a short-circuit voltage
output, or a clear state condition when CLR is low. The
power-on reset circuitry guarantees the outputs remain
off at power-up and all register bits are set to zero to
ensure a glitchless power-up sequence.
A 10MHz SPI-/QSPI-/MICROWIRE-compatible serial
interface programs the DAC outputs and configures the
device. The DOUT output allows shift-register reads or
daisy chaining of several devices. The double-buffered
interface includes an input register and a DAC register.
Use software commands or the asynchronous LDAC
input to transfer the input register contents to the DAC
register and update the DAC outputs.
The MAX5661 communicates through a serial interface
compatible with SPI, QSPI, and MICROWIRE devices.
For SPI, ensure that the SPI bus master (typically a
Outputs for Industrial Analog Output Modules
CC
4-Wire SPI-Compatible Serial Interface
) powers the digital circuitry and V
Single 16-Bit DAC with Current and Voltage
DDV
, V
______________________________________________________________________________________
SSV
Detailed Description
) for the voltage output and a
DDI
- 2.5V). The OUTI current
DDI
) for the current
DDCORE
pow-
microcontroller (µC)) runs in master mode to generate
the serial-clock signal. Set the SCLK frequency to
10MHz or less, and set the clock polarity (CPOL) and
phase (CPHA) in the µC control registers to the same
value. The MAX5661 operates with SCLK idling high or
low, and thus operates with CPOL = CPHA = 0 (see
Figure 2) or CPOL = CPHA = 1 (see Figure 3). Force
CS low to input data at DIN on the rising edge of SCLK.
Output data at DOUT updates on the falling edge of
SCLK (see Figure 1).
A high-to-low transition on CS initiates the 24-bit data
input cycle. Once CS is low, write an 8-bit command
byte (MSB first) at DIN to send data to the appropriate
internal register (see Tables 1, 2, and 3). C7 is the MSB
of the command byte and C0 is the LSB. Following the
command byte, write 2 data bytes containing bits
D15–D0. D15 is the MSB of the 2 data bytes and D0 is
the LSB (see Figure 4 and the Register Descriptions sec-
tion). Data loads into the shift register 1 bit at a time.
Write the data as one continuous 24-bit stream, always
keeping CS low throughout the entire 24-bit word. The
MAX5661 stores the 24 most recent bits received,
including bits from previous transmission(s). Ensure
SCLK has 24 rising and falling edges between CS
falling low to CS returning high. Data loads into the shift
register on the rising edge of SCLK. Once CS returns
high, data transfers from the shift register into the
appropriate internal register.
When reading data, write an 8-bit command byte and
16 data bits at DIN. On the following 24-bit sequence,
read out the shift register’s contents (command byte
and the 16 data bits) at DOUT (see Figure 5). Data tran-
sitions at DOUT on the falling edge of SCLK. While
reading data at DOUT on the second 24-bit sequence,
load another command byte and 2 data bytes at DIN or
write a no-operation command. DOUT three-states
when CS is high. The DAC outputs update on the rising
edge of CS after writing to the DAC register or by
pulling LDAC low.
Daisy chain multiple devices by connecting the first
DOUT to the second DIN, and so forth. Daisy chaining
allows communication with multiple MAX5661 devices
using single CS and SCLK signals. See the Daisy
Chaining Multiple MAX5661 Devices section.
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