MAX5661EVCMAXQU+ Maxim Integrated Products, MAX5661EVCMAXQU+ Datasheet - Page 28

• Manufacturer Part Number: MAX5661EVCMAXQU+
• Description: EVALUATION SYSTEM FOR MAX56611
• Manufacturer: Maxim Integrated Products

Specifications of MAX5661EVCMAXQU+

• Number Of Dac's: 1
• Number Of Bits: 16
• Outputs And Type: 2, Single Ended
• Data Interface: Serial
• Dac Type: Current/Voltage
• Voltage Supply Source: Single
• Operating Temperature: -40°C ~ 105°C
• Utilized Ic / Part: MAX5661
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The active-low external CLR input asynchronously sets
the DAC code to the value in the clear register (software
clear) or to the zero state (hardware clear), depending
on the control register’s CLRMODE bit setting (see
Tables 4 and 11). Set the CLRMODE bit to 1 and drive
external CLR low to force the output to the value stored
in the clear register. Set the CLRMODE bit to 0 and
drive the external CLR input low to force the output to
the zero state. The zero state value is 0mA in 0 to 20mA
current mode, 3.97mA in 4–20mA current mode, or 0V
in voltage mode (unipolar or bipolar).
Disable the external CLR input functionality by setting
the control register’s CLREN bit to 1. Set the CLREN bit
to 0 to enable the external CLR input functionality.
After setting the CLREN bit to 0, force the external CLR
input low to set the MAX5661 into the clear state. The
control register’s read-only CLEARST bit is set to 1 while
in the clear state. The RCLR (remain in clear) bit deter-
mines the steps required to exit the clear state.
With the RCLR bit set to 1, exit the clear state in one of
three ways:
1) Pull the external CLR input high and then write to
2) Pull the external CLR input high and set the RCLR
3) Initiate a power-on reset (POR) to reset the RCLR bit
Single 16-Bit DAC with Current and Voltage
Outputs for Industrial Analog Output Modules
Table 11. Hardware-Clear and Software-Clear Truth Table
X = Don’t care.
* Zero state is 0V in unipolar voltage mode, -10.48V in bipolar voltage mode, and 0mA/4mA depending on output-current mode.
28
the DAC register (0x04) or the load DAC register
(0x05) or force LDAC low.
bit low.
to 0.
_______________________________________________________________________________________
0 (not in clear state)
1 (in clear state)
1 (in clear state)
CLEARST BIT
(READ)
CLRMODE BIT
(READ/WRITE)
X
0
1
CLR Input
DAC code set to zero state*
HARDWARE CLEAR
With the RCLR bit set to 0, exit the clear state one of
three ways:
1) Set the CLREN bit high.
2) Pull the external CLR input high.
3) Initiate a power-on reset (POR).
The open-drain active-low FAULT output asserts low for
a current-output open circuit or dropout condition, for a
voltage-output short circuit, or when the MAX5661 is in
the clear state (see the CLR Input section).
Enable and disable the FAULT output with the control
register’s FAULTEN and CLRFLAGEN bits (see Tables
4, 12, and Figure 9). Set the FAULTEN bit to 1 to enable
the FAULT output to report fault conditions on OUTV
and OUTI. Set FAULTEN to 0 to disable the FAULT out-
put for fault conditions on OUTV and OUTI. Set the
CLRFLAGEN bit to 1 to enable the FAULT output
to report when the device is in the clear state. Set
CLRFLAGEN to 0 to disable a hardware indication
of the clear state. The FAULT output asserts low if
CLRFLAGEN = 1 and CLEARST = 1.
Read the control register to determine the source of
a FAULT output condition. The FAULTV read-only bit
is set to 1 when the voltage output (OUTV) is short-
circuited. The FAULTI bit is set to 1 when the current
output (OUTI) is open circuited or in a dropout condition
(V
low if FAULTEN is set to 1 and either the FAULTV bit or
FAULTI bit is set to 1.
DDI
- V
—
X
OUTI
at 1.3V typ). The FAULT output asserts
DAC code set by clear register data
SOFTWARE CLEAR
FAULT Output
—
X