LP5521TMEV National Semiconductor, LP5521TMEV Datasheet - Page 23

• Manufacturer Part Number: LP5521TMEV
• Description: EVAL BOARD FOR LP5521
• Manufacturer: National Semiconductor

Specifications of LP5521TMEV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5109809

Logic Interface Operational Description
LP5521 features a flexible logic interface for connecting to
processor and peripheral devices. Communication is done
with I
pins makes it possible to synchronize operation of several
devices.
IO Levels
I
fined by EN pin. Using EN pin as voltage reference for logic
inputs simplifies PWB routing and eliminates the need for
dedicated V
EN pin connections.
ADDR_SEL0/1 are referenced to V
is defined by V
GPO/INT pins
LP5521 has one General Purpose Output pin (GPO) and also
INT pin can be configured as a GPO pin. When INT is con-
figured as GPO output, it's level is defined by the V
State of the pins can be controlled with GPO register (0EH).
GPO pins are digital CMOS outputs and no pull-up/down re-
sistors are needed.
When INT pin GPO function is disabled, it operates as an
open drain pin. INT signal is active low, i.e. when interrupt
signal is sent, the pin is pulled to GND. External pull-up re-
sistor is needed for proper functionality.
2
C interface, CLK_32K and TRIG pins input levels are de-
2
C compatible interface and different logic input/output
Using EN pin as digital IO voltage reference
IO
pin. In the following block diagram is described
DD
voltage.
DD
voltage. GPO pin level
20186254
DD
voltage.
23
TRIG pin
TRIG pin can function as an external trigger input or output.
External trigger signal is active low, i.e. when trigger is sent/
received the pin is pulled to GND. TRIG is an open drain pin
and external pull-up resistor is needed for trigger line. Exter-
nal trigger input signal must be at least two 32 kHz clock
cycles long to be recognized. Trigger output signal is three 32
kHz clock cycles long. If TRIG pin is not used on application,
it should be connected to GND to prevent floating of this pin
and extra current consumption.
ADDR_SEL0,1 pins
ADDR_SEL0,1 pins define the chip I
erenced to V
Interface chapter for I
CLK_32K pin
CLK_32K pin is used for connecting external 32 kHz clock to
LP5521. External clock can be used to synchronize the se-
quence engines of several LP5521. Using external clock can
also improve automatic power save mode efficiency, because
internal clock can be switched off automatically when device
has entered power save mode, and external clock is present.
See application note “LP5521 Power Efficiency Consider-
ations” for more information.
Device can be used without the external clock. If external
clock is not used on the application, CLK_32K pin should be
connected to GND to prevent floating of this pin and extra
current consumption.
INT_AS_GPO
Name
GPO
INT
DD
signal level. See I
Bit Description
2
1
0
GPO register (0EH)
2
C address definitions.
Enable INT pin GPO function
0 = INT pin functions as a INT pin
1 = INT pin functions as a GPO pin
0 = GPO pin state is low
1 = GPO pin state is high
0 = INT pin state is low
(INT_AS_GPO=1)
1 = INT pin state is high
(INT_AS_GPO=1)
2
C Compatible Serial Bus
2
C address. Pins are ref-
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