LP5521TMEV National Semiconductor, LP5521TMEV Datasheet - Page 8

• Manufacturer Part Number: LP5521TMEV
• Description: EVAL BOARD FOR LP5521
• Manufacturer: National Semiconductor

Specifications of LP5521TMEV

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q5109809

www.national.com
I
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation
of the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions,
see the Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T
= 130°C (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note AN1112 : Micro SMD Wafer Level Chip
Scale Package or AN1187 : Leadless Leadframe Package (LLP).
Note 5: The Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged
directly into each pin. MIL-STD-883 3015.7
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (T
dissipation of the device in the application (P
following equation: T
Note 7: Junction-to-ambient thermal resistance is highly application and board-layout dependent. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design.
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics.
Note 10: Input, output, and fly capacitors should be of the type X5R or X7R low ESR ceramic capacitor.
Note 11: Matching is the maximum difference from the average of the three output's currents.
Note 12: Saturation voltage is defined as the voltage when the LED current has dropped 10% from the value measured at V
Note 13: Guaranteed by design.
2
Symbol
C Timing Parameters (SDA, SCL)
f
SCL
10
C
1
2
3
4
5
6
7
8
9
b
Clock Frequency
Hold Time (repeated) START Condition
Clock Low Time
Clock High Time
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Rise Time of SDA and SCL
Fall Time of SDA and SCL
Set-up Time for STOP condition
Bus Free Time between a STOP and a START Condition
Capacitive Load for Each Bus Line
A-MAX
= T
J-MAX-OP
– (θ
JA
A-MAX
× P
D-MAX
D-MAX
) is dependent on the maximum operating junction temperature (T
), and the junction-to ambient thermal resistance of the part/package in the application (θ
Parameter
).
(Note 13)
8
20+0.1C
15+0.1C
Min
600
600
100
600
0.6
1.3
1.3
50
10
J-MAX-OP
b
b
Limit
J
= 125°C), the maximum power
= 150°C (typ.) and disengages at T
OUT
- 1V.
Max
400
300
300
200
20186298
JA
), as given by the
Units
kHz
µs
µs
ns
ns
ns
ns
ns
ns
ns
µs
pF
J