ISL28168EVAL1Z Intersil, ISL28168EVAL1Z Datasheet - Page 11

• Manufacturer Part Number: ISL28168EVAL1Z
• Description: EVALUATION BOARD FOR ISL28168
• Manufacturer: Intersil

Specifications of ISL28168EVAL1Z

• Channels Per Ic: 1 - Single
• Amplifier Type: General Purpose
• Output Type: Single-Ended, Rail-to-Rail
• Slew Rate: 0.1 V/µs
• -3db Bandwidth: 420kHz
• Current - Output / Channel: 30mA
• Operating Temperature: -40°C ~ 125°C
• Current - Supply (main Ic): 34µA
• Voltage - Supply, Single/dual (±): 2.4 V ~ 5.5 V, ±1.2 V ~ 2.75 V
• Board Type: Fully Populated
• Utilized Ic / Part: ISL28168
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Pin Descriptions
Applications Information
Introduction
The ISL28168 is a single CMOS rail-to-rail input, output
(RRIO) operational amplifier with an enable feature. The
ISL28268 is a dual version without the enable feature. Both
devices are designed to operate from single supply (2.4V to
5.5V) or dual supplies (±1.2V to ±2.75V).
Rail-to-Rail Input/Output
Many rail-to-rail input stages use two differential input pairs,
a long-tail PNP (or PFET) and an NPN (or NFET). Severe
penalties have to be paid for this circuit topology. As the
input signal moves from one supply rail to another, the
operational amplifier switches from one input pair to the
other causing drastic changes in input offset voltage and an
(6 Ld SOT-23)
ISL28168
4
3
2
1
6
5
(8 Ld MSOP)
(8 Ld SOIC)
ISL28268
2 (A)
6 (B)
3 (A)
5 (B)
1 (A)
7 (B)
4
8
11
PIN NAME
OUT_A
OUT_B
IN+_A
IN+_B
IN-_A
IN-_B
OUT
IN+
IN-
EN
V+
V-
ISL28168, ISL28268
Inverting input
Non-inverting input
Negative supply
Output
Positive supply
Chip enable
FUNCTION
undesired change in magnitude and polarity of input offset
current.
The ISL28168 and ISL28268 achieve input rail-to-rail
operation without sacrificing important precision
specifications and degrading distortion performance. The
devices’ input offset voltage exhibits a smooth behavior
throughout the entire common-mode input range. The input
bias current versus the common-mode voltage range gives
us an undistorted behavior from typically 100mV below the
negative rail, and 0.25V higher than the V+ rail. The CMOS
output stage features excellent drive capability, typically
swinging to within 6mV of either rail with a 100kΩ load.
IN-
V+
LOGIC
V-
PIN
EQUIVALENT CIRCUIT
See Circuit 1
See Circuit 2
CIRCUIT 1
CIRCUIT 2
CIRCUIT 3
CIRCUIT 3
CAPACITIVELY
COUPLED
ESD CLAMP
V-
V+
OUT
V+
V-
V+
IN+
V-
June 30, 2008
FN6378.3