STEVAL-IFS012V1 STMicroelectronics, STEVAL-IFS012V1 Datasheet - Page 96

BOARD ST72651AR6/STTS75/STLM20

STEVAL-IFS012V1

Manufacturer Part Number
STEVAL-IFS012V1
Description
BOARD ST72651AR6/STTS75/STLM20
Manufacturer
STMicroelectronics
Datasheets

Specifications of STEVAL-IFS012V1

Sensor Type
Temperature
Sensing Range
Depends on IC
Interface
I²C, USB
Sensitivity
Depends on IC
Voltage - Supply
5V
Embedded
Yes, MCU, 8-Bit
Utilized Ic / Part
ST72F651AR6, STTS75, STLM20
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-8419

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
STEVAL-IFS012V10
Manufacturer:
ST
0
ST72651AR6
SERIAL PERIPHERAL INTERFACE (Cont’d)
11.6.3.2 Slave Select Management
As an alternative to using the SS pin to control the
Slave Select signal, the application can choose to
manage the Slave Select signal by software. This
is configured by the SSM bit in the SPICSR regis-
ter (see
In software management, the external SS pin is
free for other application uses and the internal SS
signal level is driven by writing to the SSI bit in the
SPICSR register.
In Master mode:
Figure 57. Generic SS Timing Diagram
Figure 58. Hardware/Software Slave Select Management
96/161
– SS internal must be held high continuously
MOSI/MISO
(if CPHA=0)
(if CPHA=1)
Figure
Master SS
Slave SS
Slave SS
58)
SS external pin
SSI bit
Byte 1
Doc ID 7215 Rev 4
SSM bit
1
0
In Slave Mode:
There are two cases depending on the data/clock
timing relationship (see
If CPHA=1 (data latched on 2nd clock edge):
If CPHA=0 (data latched on 1st clock edge):
SS internal
Byte 2
– SS internal must be held low during the entire
– SS internal must be held low during byte
transmission. This implies that in single slave
applications the SS pin either can be tied to
V
ing the SS function by software (SSM= 1 and
SSI=0 in the in the SPICSR register)
transmission and pulled high between each
byte to allow the slave to write to the shift reg-
ister. If SS is not pulled high, a Write Collision
error will occur when the slave writes to the
shift register (see
SS
, or made free for standard I/O by manag-
Byte 3
Section
Figure
11.6.5.3).
57):

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