DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 14

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

1–14
Ordering Information
Figure 1–1. Stratix III Device Packaging Ordering Information
Chapter Revision History
Table 1–6. Chapter Revision History (Part 1 of 2)
Stratix III Device Handbook, Volume 1
March 2010
May 2009
February 2009
October 2008
EP3SL:
EP3SE:
F: FineLine BGA (FBGA)
H: Hybrid FineLine BGA (HBGA)
50
70
80
110
150
200
260
340
Package Type
Device Type
Family S i g n a t u r e
Date
Stratix III Logic
Stratix III DSP/Memory
f
Figure 1–1
For more information about a specific package, refer to the
Information
Table 1–6
Version
1.8
1.7
1.6
1.5
EP3SL
lists the revision history for this chapter.
150
shows the ordering codes for Stratix III devices.
chapter.
Updated “Software” and “Signal Integrity” sections.
Updated for the Quartus II software version 9.1 SP2 release:
■
■
■
■
■
■
■
■
Updated
Updated
Updated “Features” section.
Updated Table 1–1.
Removed “Referenced Documents” section.
Updated “Features” section.
Updated Table 1–1 and Table 1–5.
Updated New Document Format.
F
Table
“I/O Banks and I/O Structure”
Number of pins for a particular package:
484
780
1152
1517
1760
1152
Pi n Count
1–2.
C
2
Changes Made
ES
section.
ES: Engineering sample
L: Low-voltage devices
Chapter 1: Stratix III Device Family Overview
Indicates specific device options
N: Lead-free devices
2, 3, or 4, with 2 being the fastest
C: Commercial temperature (t
I :
Operating Temperature
Speed Grade
Optional Suffix
Industrial temperature (t
Stratix III Device Package
© March 2010 Altera Corporation
Chapter Revision History
J
= - 40 C to 100 C)
J
= 0 C to 85 C)