DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 3

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 1: Stratix III Device Family Overview
Features Summary
Table 1–1. FPGA Family Features for Stratix III Devices
© March 2010 Altera Corporation
Stratix III
Logic
Family
Stratix III
Enhanced
Family
Notes to
(1) MLAB ROM mode supports twice the number of MLAB RAM Kbits.
(2) For total ROM Kbits, use this equation to calculate:
(3) The availability of the PLLs shown in this column is based on the device with the largest package. Refer to the
Total ROM Kbits = Total Embedded RAM Kbits + [(# of MLAB blocks × 640)/1024]
III Devices
Table
chapter in volume 1 of the Stratix III Device Handbook for the availability of the PLLs for each device.
1–1:
EP3SL50
EP3SL70
EP3SL110
EP3SL150
EP3SL200
EP3SL340
EP3SE50
EP3SE80
EP3SE110
EP3SE260
Feature
Device/
Table 1–1
The Stratix III logic family (L) offers balanced logic, memory, and multipliers to
address a wide range of applications, while the enhanced family (E) offers more
memory and multipliers per logic and is ideal for wireless, medical imaging, and
military applications.
Stratix III devices are available in space-saving FineLine BGA (FBGA) packages (refer
to
Table 1–2
ALMs
135K 337.5K
102K
19K
27K
43K
57K
80K
19K
32K
43K
lists the Stratix III FPGA family features.
107.5K
142.5K
107.5K
47.5K
67.5K
47.5K
200K
255K
80K
LEs
and
Table
Blocks
1,040
M9K
108
150
275
355
468
400
495
639
864
1–3).
M144K
Blocks
12
16
36
48
12
12
16
48
6
6
Blocks
MLAB
1,350
2,150
2,850
4,000
6,750
1,600
2,150
5,100
950
950
Embedded
RAM Kbits
16,272
14,688
1,836
2,214
4,203
5,499
9,396
5,328
6,183
8,055
Total
MLAB
1,250
2,109
1,594
Kbits
RAM
297
422
672
891
297
500
672
(1)
Stratix III Device Handbook, Volume 1
Clock Networks and PLLs in Stratix
Kbits(2)
10,646
18,381
16,282
2,133
2,636
4,875
6,390
5,625
6,683
8,727
Total
RAM
Multipliers
(FIR Mode)
18×18-bit
216
288
288
384
576
576
384
672
896
768
1–3
PLLs
(3)
12
12
12
4
4
8
8
4
8
8