XE8000EV104 Semtech, XE8000EV104 Datasheet - Page 52

• Manufacturer Part Number: XE8000EV104
• Description: EVAL BOARD FOR XE8805AMI028LF
• Manufacturer: Semtech
• Type: MCUr

Specifications of XE8000EV104

• Contents: Fully Assembled Evaluation Board
• For Use With/related Products: XE88LC05AMI028
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.1 Features
The XE8000 chips support 24 interrupt sources, divided into 3 levels of priority.
8.2 Overview
A CPU interruption is generated and memorized when an interrupt becomes active. The 24 interrupt sources are
divided into 3 levels of priority: High (8 interrupt sources), Mid (8 interrupt sources), and Low (8 interrupt sources).
Those 3 levels of priority are directly mapped to those supported by the CoolRisc® (IN0, IN1 and IN2; see
CoolRisc® documentation for more information).
RegIrqHig, RegIrqMid, and RegIrqLow are 8-bit registers containing flags for the interrupt sources. Those flags
are set when the interrupt is enabled (i.e. if the corresponding bit in the registers RegIrqEnHig, RegIrqEnMid or
RegIrqEnLow is set) and a rising edge is detected on the corresponding interrupt source.
Once memorized, an interrupt flag can be cleared by writing a ‘1’ in the corresponding bit of RegIrqHig, RegIrqMid
or RegIrqLow. Writing a ‘0’ does not modify the flag. To definitively clear the interrupt, one has to clear the
CoolRisc interrupt in the CoolRisc status register. All interrupts are automatically cleared after a reset.
Two registers are provided to facilitate the writing of interrupt service software. RegIrqPriority contains the number
of the highest priority interrupt set (its value is 0xFF when no interrupt is set). RegIrqIrq indicates the priority level
of the current interrupts. RegIrqIrq and RegIrqPriority ‘s values are dependent upon the memorized state of the
interrupts (as reflected in flags in RegIrqHig, RegIrqMid and RegIrqLow).
8.3 Register map
© Semtech 2006
7
6
5
4
3
2
1
0
pos.
RegIrqHig[7]
RegIrqHig[6]
RegIrqHig[5]
RegIrqHig[4]
RegIrqHig[3]
RegIrqHig[2]
RegIrqHig[1]
RegIrqHig[0]
RegIrqHig
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
r
c1
rw
Table 8-1: RegIrqHig
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
0 resetsystem
reset
8-2
interrupt #23 (high priority)
interrupt #22 (high priority)
interrupt #21 (high priority)
interrupt #20 (high priority)
interrupt #19 (high priority)
interrupt #18 (high priority)
interrupt #17 (high priority)
interrupt #16 (high priority)
clear interrupt #23 when 1 is written
clear interrupt #22 when 1 is written
clear interrupt #21 when 1 is written
clear interrupt #20 when 1 is written
clear interrupt #19 when 1 is written
clear interrupt #18 when 1 is written
clear interrupt #17 when 1 is written
clear interrupt #16 when 1 is written
function
XE8805/05A
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