C8051T600DK Silicon Laboratories Inc, C8051T600DK Datasheet - Page 107

• Manufacturer Part Number: C8051T600DK
• Description: KIT DEV FOR C8051T60X MCU'S
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051T600DK

• Contents: Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
• Processor To Be Evaluated: C8051T60x
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051T600, C8051T601, C8051T602, C8051T603, C8051T604, C8051T605
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1404

22.1. Port I/O Modes of Operation
Port pins use the Port I/O cell shown in Figure 22.2. Each Port I/O cell can be configured by software for
analog I/O or digital I/O using the P0MDIN registers. On reset, all Port I/O cells default to a high impedance
state with weak pull-ups enabled until the crossbar is enabled (XBARE = 1).
22.1.1. Port Pins Configured for Analog I/O
Any pins to be used as inputs to the comparator, ADC, external oscillator, or VREF should be configured
for analog I/O (P0MDIN.n = 0). When a pin is configured for analog I/O, its weak pullup, digital driver, and
digital receiver are disabled. Port pins configured for analog I/O will always read back a value of 0.
Configuring pins as analog I/O saves power and isolates the Port pin from digital interference. Port pins
configured as digital inputs may still be used by analog peripherals; however, this practice is not recom-
mended and may result in measurement errors.
22.1.2. Port Pins Configured For Digital I/O
Any pins to be used by digital peripherals (UART, SMBus, PCA, etc.), external digital event capture func-
tions, or as GPIO should be configured as digital I/O (P0MDIN.n = 1). For digital I/O pins, one of two output
modes (push-pull or open-drain) must be selected using the P0MDOUT registers.
Push-pull outputs (P0MDOUT.n = 1) drive the Port pad to the VDD or GND supply rails based on the out-
put logic value of the Port pin. Open-drain outputs have the high side driver disabled; therefore, they only
drive the Port pad to GND when the output logic value is 0 and become high impedance inputs (both high
and low drivers turned off) when the output logic value is 1.
When a digital I/O cell is placed in the high impedance state, a weak pull-up transistor pulls the Port pad to
the VDD supply voltage to ensure the digital input is at a defined logic state. Weak pull-ups are disabled
when the I/O cell is driven to GND to minimize power consumption and may be globally disabled by setting
WEAKPUD to 1. The user should ensure that digital I/O are always internally or externally pulled or driven
to a valid logic state to minimize power consumption. Port pins configured for digital I/O always read back
the logic state of the Port pad, regardless of the output logic value of the Port pin.
WEAKPUD
(Weak Pull-Up Disable)
Px.x – Output
Logic Value
(Port Latch or
Crossbar)
PxMDOUT.x
(1 for push-pull)
(0 for open-drain)
XBARE
(Crossbar
Enable)
Px.x – Input Logic Value
(Reads 0 when pin is configured as an analog I/O)
To/From Analog
Peripheral
PxMDIN.x
(1 for digital)
(0 for analog)
Figure 22.2. Port I/O Cell Block Diagram
Rev. 1.2
C8051T600/1/2/3/4/5/6
VDD
GND
VDD
(WEAK)
PORT
PAD
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