EA-OEM-315 Embedded Artists, EA-OEM-315 Datasheet - Page 11

• Manufacturer Part Number: EA-OEM-315
• Description: KIT LPC3141 SODIMM 66X48 200POS
• Manufacturer: Embedded Artists
• Type: MCUr

Specifications of EA-OEM-315

• Contents: Board
• For Use With/related Products: LPC3141
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
[1]
[2]
[3]
[4]
[5]
[6]
[7]
LPC3141_3143
Preliminary data sheet
Pin name
EBI_D_5
EBI_D_6
EBI_D_7
EBI_D_8
EBI_D_9
EBI_D_10
EBI_D_11
EBI_D_12
EBI_D_13
EBI_D_14
EBI_D_15
EBI_DQM_0_NOE
EBI_NWE
NAND_NCS_0
NAND_NCS_1
NAND_NCS_2
NAND_NCS_3
mNAND_RYBN0
mNAND_RYBN1
mNAND_RYBN2
mNAND_RYBN3
EBI_NCAS_BLOUT_0
EBI_NRAS_BLOUT_1
Secure one-time programmable memory
VPP
Pulse Width Modulation (PWM)
PWM_DATA
Digital IO levels are explained in
I = input; I:PU = input with internal weak pull-up; I:PD = input with internal weak pull-down; O = output.
Cell types are explained in
Pin can be configured as GPIO pin in the IOCONFIG block.
The UART flow control lines (mUART_CTS_N and mUART_RTS_N) are multiplexed. This means that if these balls are not required for
UART flow control, they can be selected to be used for alternative functions: SPI chip select signals (SPI_CS_OUT1 and
SPI_CS_OUT2).
The polyfuses get unintentionally burned at random if VPP is powered to 2.3 V or greater before the VDDI is powered up to minimum
nominal voltage. This will destroy the sample because randomly blowing security fuses will lock the sample and also can corrupt the
AES key. For this reason it is recommended that VPP be powered by SUP1 at power on.
To ensure that GPIO0, GPIO1 and GPIO2 pins come up as inputs, pins TRST_N and JTAGSEL must be LOW at power-on reset, see
UM10362 JTAG chapter for details.
[6]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
Pin description
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
[4]
BGA
Ball
D1
D2
C1
B1
A3
A1
C2
G3
D3
E3
F3
H1
J2
J1
J3
K1
K2
E6
E7
B4
D4
G1
H2
A9;
C9
B9
Table
…continued
Table
6.
Digital
I/O
level
[1]
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP4
SUP1/
SUP3
SUP3
5.
All information provided in this document is subject to legal disclaimers.
Application
function
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DIO
DO
DO
DO
DO
DO
DO
DI
DI
DI
DI
DO
DO
Supply
DO/GPIO
Rev. 0.16 — 27 May 2010
Table 10
Pin
state
after
reset
I
I
I
I
I
I
I
I
I
I
I
O
O
O
O
O
O
I
I
I
I
O
O
-
O
for pin function selection of multiplexed pins.
[2]
Cell type
[3]
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
DIO4
PS3
DIO1
Description
EBI data I/O 5.
EBI data I/O 6.
EBI data I/O 7.
EBI data I/O 8.
EBI data I/O 9.
EBI data I/O 10.
EBI data I/O 11.
EBI data I/O 12.
EBI data I/O 13.
EBI data I/O 14.
EBI data I/O 15.
NAND read enable (active LOW).
NAND write enable (active LOW).
NAND chip enable 0.
NAND chip enable 1.
NAND chip enable 2.
NAND chip enable 3.
NAND ready/busy 0.
NAND ready/busy 1.
NAND ready/busy 2.
NAND ready/busy 3.
EBI lower lane byte select (7:0).
EBI upper lane byte select (15:8).
Supply for polyfuse programming.
PWM output.
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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