ATSAM3S-EK Atmel, ATSAM3S-EK Datasheet - Page 75
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ATSAM3S-EK
Manufacturer Part Number
ATSAM3S-EK
Description
KIT EVAL FOR ATSAM3S4C
Manufacturer
Atmel
Series
SAM3Sr
Type
MCUr
Specifications of ATSAM3S-EK
Contents
Board, Cables, Power Supply
Silicon Manufacturer
Atmel
Core Architecture
ARM
Core Sub-architecture
Cortex-M3
Kit Contents
Board
Features
TFT Colour LCD Display, SD/MMC Interface
Svhc
No SVHC (15-Dec-2010)
Rohs Compliant
Yes
For Use With/related Products
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATSAM3S-EK
Manufacturer:
Atmel
Quantity:
135
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- Download datasheet (24Mb)
10.9
6500C–ATARM–8-Feb-11
Instruction set summary
The processor implements a version of the Thumb instruction set.
ported instructions.
In
For more information on the instructions and operands, see the instruction descriptions.
Table 10-13. Cortex-M3 instructions
Mnemonic
ADC, ADCS
ADD, ADDS
ADD, ADDW
ADR
AND, ANDS
ASR, ASRS
B
BFC
BFI
BIC, BICS
BKPT
BL
BLX
BX
CBNZ
CBZ
CLREX
CLZ
CMN, CMNS
CMP, CMPS
CPSID
CPSIE
DMB
DSB
EOR, EORS
• angle brackets, <>, enclose alternative forms of the operand
• braces, {}, enclose optional operands
• the Operands column is not exhaustive
• Op2 is a flexible second operand that can be either a register or a constant
• most instructions can use an optional condition code suffix.
Table
10-13:
Operands
{Rd,} Rn, Op2
{Rd,} Rn, Op2
{Rd,} Rn, #imm12
Rd, label
{Rd,} Rn, Op2
Rd, Rm, <Rs|#n>
label
Rd, #lsb, #width
Rd, Rn, #lsb, #width
{Rd,} Rn, Op2
#imm
label
Rm
Rm
Rn, label
Rn, label
-
Rd, Rm
Rn, Op2
Rn, Op2
iflags
iflags
-
-
{Rd,} Rn, Op2
Brief description
Add with Carry
Add
Add
Load PC-relative address
Logical AND
Arithmetic Shift Right
Branch
Bit Field Clear
Bit Field Insert
Bit Clear
Breakpoint
Branch with Link
Branch indirect with Link
Branch indirect
Compare and Branch if Non Zero
Compare and Branch if Zero
Clear Exclusive
Count leading zeros
Compare Negative
Compare
Change Processor State, Disable
Interrupts
Change Processor State, Enable
Interrupts
Data Memory Barrier
Data Synchronization Barrier
Exclusive OR
SAM3S Preliminary
Table 10-13
Flags
N,Z,C,V
N,Z,C
-
-
-
-
-
N,Z,C,V
N,Z,C,V
-
-
-
-
N,Z,C,V
N,Z,C,V
-
N,Z,C
-
-
N,Z,C
-
-
-
-
N,Z,C
lists the sup-
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75
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