EVAL-ADUC7039QSPZ Analog Devices Inc, EVAL-ADUC7039QSPZ Datasheet
EVAL-ADUC7039QSPZ
Specifications of EVAL-ADUC7039QSPZ
Related parts for EVAL-ADUC7039QSPZ
EVAL-ADUC7039QSPZ Summary of contents
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FEATURES High precision ADC Dual channel, simultaneous sampling, 16-bit, Σ-Δ ADCs Programmable ADC throughput from kHz On-chip 5 ppm/ºC voltage reference Current channel Fully differential, buffered input Programmable gain ADC input range: −200 mV to +300 ...
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ADuC7039 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Electrical Specifications ............................................................... 3 Timing Specifications .................................................................. 7 Absolute Maximum Ratings ............................................................ 8 ESD Caution .................................................................................. 8 Pin ...
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SPECIFICATIONS ELECTRICAL SPECIFICATIONS 1.2 V internal reference REF +115°C, unless otherwise noted. Table 1. Parameter Test Conditions/Comments ADC SPECIFICATIONS 1 Conversion Rate ADC normal operating mode ADC low power ...
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ADuC7039 Parameter Test Conditions/Comments ADC SPECIFICATIONS, ANALOG INPUT Current Channel 1 Absolute Input Voltage Range Applies to both IIN+ and IIN− Input Voltage Range Gain = 4 Gain = 8 Gain = 32 Gain = 512 1 ...
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Parameter Test Conditions/Comments 1 LOGIC INPUTS All logic inputs Input Low Voltage (VINL) Input High Voltage (VINH) ON-CHIP OSCILLATORS Low Power Oscillator Accuracy After user calibration at nominal supply and room temperature; includes drift data from 1000 hr life-test Precision ...
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ADuC7039 Parameter Test Conditions/Comments REC(MAX) TH DOM(MAX 7.0 V ... μs BIT REC(min) TH DOM(min 7.0 V … 18 ...
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TIMING SPECIFICATIONS LIN Timing Specifications RECESSIVE TRANSMIT INPUT TO TRANSMITTING NODE DOMINANT TH REC (MAX) TH DOM (MAX) V SUP (TRANSCEIVER SUPPLY OF TRANSMITTING NODE) TH REC (MIN) TH DOM (MIN) RxD (OUTPUT OF RECEIVING NODE 1) RxD (OUTPUT OF ...
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ADuC7039 ABSOLUTE MAXIMUM RATINGS T = −40°C to +115°C, unless otherwise noted. A Table 2. Parameter Rating AGND to DGND to VSS to IO_VSS −0 +0.3 V VBAT to AGND − +40 V VDD to VSS ...
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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 3. Pin Function Descriptions 1 Pin No. Mnemonic Type Description 1 RESET I Reset Input Pin. Active low. This pin has an internal, weak, pull-up resistor to REG_DVDD. When not in use, this pin ...
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ADuC7039 1 Pin No. Mnemonic Type Description 21 GPIO_0/SS I/O General-Purpose Digital I SPI Interface. By default, this pin is configured as an input. The pin has an internal, weak, pull-up resistor and, when not in use, can ...
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TERMINOLOGY Conversion Rate The conversion rate specifies the rate at which an output result is available from the ADC, after the ADC has settled. The sigma-delta (Σ-Δ) conversion techniques used on this part mean that while the ADC front-end signal ...
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ADuC7039 THEORY OF OPERATION The ADuC7039 is a complete system solution for battery moni- toring automotive applications. This device integrates all of the required features to precisely and intelligently monitor, process, and diagnose 12 V battery parameters ...
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ARM7 Exceptions The ARM7 supports five types of exceptions, with a privileged processing mode associated with each type. The five types of exceptions are as follows: • Normal interrupt or IRQ. This is provided to service general-purpose interrupt handling of ...
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ADuC7039 MEMORY ORGANIZATION The ARM7, a von Neumann architecture, MCU core sees mem- 32 ory as a linear array of 2 byte locations. As shown in Figure 5, the ADuC7039 maps this into four distinct user areas, namely: a memory ...
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The remap command must be executed from the absolute Flash/EE address, and not from the mirrored, remapped segment of memory, because this may be replaced by SRAM remap operation is executed while operating code from the mirrored location, ...
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ADuC7039 FLASH/EE MEMORY The ADuC7039 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogrammable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be erased, the ...
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FEECON Register Name: FEECON Address: 0xFFFF0E08 Default Value: 0x07 Access: Read/write Function: This 8-bit register is written by user code to control the operating modes of the Flash/EE memory controller. Table 10. Command Codes in FEECON Code Command 1 0x00 ...
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ADuC7039 Command Sequence for Executing a Mass Erase Given the significance of the mass erase command, a specific code sequence must be executed to initiate this operation. 1. Ensure FEESTA is cleared. 2. Set Bit 3 in FEEMOD. 3. Write ...
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FEEMOD Register Name: FEEMOD Address: 0xFFFF0E04 Default Value: 0x0000 Access: Read/write Function: This register is written by user code to configure the mode of operation of the Flash/EE memory controller. Table 12. FEEMOD MMR Bit Designation Bit Description 15 to ...
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ADuC7039 FLASH/EE MEMORY SIGNATURE The entire the part of Flash/EE memory available to the user can be signed using the FEESIG register and signature command. This feature automatically reads the code in that section of the memory ...
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FLASH/EE MEMORY SECURITY The Flash/EE memory available to the user can be read- and write-protected using the FEEHID register. The MSB of FEEHID (Bit 31) protects the entire Flash/EE from being read through JTAG. Bits[30:0] of FEEHID ...
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ADuC7039 In summary, there are three levels of protection as follows. Temporary Protection Temporary protection can be set and removed by writing directly into FEEHID MMR. This register is volatile and, therefore, protection is only in place for as long ...
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FLASH/EE MEMORY RELIABILITY The Flash/EE memory array on the part is fully qualified for two key Flash/EE memory characteristics: Flash/EE memory cycling endurance and Flash/EE memory data retention. Endurance quantifies the ability of the Flash/EE memory to be cycled through ...
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ADuC7039 Normal kernel execution time, excluding LIN download, is less than 5 ms only possible to enter and leave LIN download mode through a reset. SRAM Address 0 to Address 0x2B are modified during normal kernel execution, SRAM ...
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MEMORY MAPPED REGISTERS (MMR) The memory mapped register (MMR) space is mapped into the top the MCU memory space and accessed by indirect addressing, load, and store commands through the ARM7 banked registers. An outline of the ...
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ADuC7039 COMPLETE MMR LISTING In the following MMR tables, addresses are listed in hex code. Access types include R for read, W for write, and RW for read and write. Table 14. IRQ Address Base = 0xFFFF0000 Access Address Name ...
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Table 17. PLL Base Address = 0xFFFF0400 Access Address Name Byte Type 0x0400 PLLSTA 4 R 0x0404 POWKEY0 4 W 0x0408 POWCON 2 RW 0x040C POWKEY1 4 W 0x0410 PLLKEY0 4 W 0x0414 PLLCON 1 RW 0x0418 PLLKEY1 4 W ...
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ADuC7039 Table 19. LIN Base Address = 0XFFFF0700 Access Address Name Byte Type 0x0700 LINCON 2 RW 0x0704 LINCS 1 RW 0x0708 LINBR 3 RW 0x070C LINBK 3 RW 0x0710 LINSTA 2 R 0x0714 LINDAT 1 RW 0x0718 LINLOW 3 ...
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SIGMA-DELTA ANALOG-TO-DIGITAL CONVERTERS The ADuC7039 incorporates two independent sigma-delta (Σ-Δ) analog-to-digital converters (ADCs) namely, the current channel ADC (I-ADC), and the voltage/temperature channel ADC (V/T-ADC). These precision measurement channels integrate attenuator, on-chip buffering, a programmable gain amplifier, 16-bit, Σ-Δ ...
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ADuC7039 Figure 11. Current ADC, Top Level Overview Rev Page 08463-012 ...
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Voltage/Temperature Channel ADC (V/T-ADC) The voltage/temperature channel ADC (V/T-ADC) converts additional battery parameters such as voltage and temperature. The input to this channel can be multiplexed from an external voltage and an on-chip temperature sensor. As with the current channel ...
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ADuC7039 ADC GROUND SWITCH The ADuC7039 features an integrated ground switch pin, GND_SW, Pin 9. This switch allows the user to dynamically disconnect ground from external devices and allows a connec- tion to ground using a 20 kΩ resistor, reducing ...
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ADC MMR INTERFACE The ADC is controlled and configured through a number of MMRs that are described in detail in the following sections. All bits defined in the top eight MSBs (Bits[15:8]) of the ADCSTA MMR are used as flags ...
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ADuC7039 ADC Interrupt Mask Register Name: ADCMSKI Address: 0xFFFF0504 Default Value: 0x00 Access: Read/write Function: This register allows the ADC interrupt sources to be individually enabled. The bit positions in this register are the same as the lower eight bits ...
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Current Channel ADC Control Register Name: ADC0CON Address: 0xFFFF050C Default Value: 0x0002 Access: Read/write Function: The current channel ADC control MMR is a 16-bit register that is used to configure the I-ADC. Note: If the current ADC is reconfigured via ...
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ADuC7039 Voltage/Temperature Channel ADC Control Register Name: ADC1CON Address: 0xFFFF0510 Default Value: 0x0000 Access: Read/write Function: The voltage/temperature channel ADC control MMR is a 16-bit register that is used to configure the V/T-ADC. If both ADCs are being reconfigured, ADC1CON ...
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ADC Filter Register Name: ADCFLT Address: 0xFFFF0518 Default Value: 0x0007 Access: Read/write Function: The ADC filter MMR is a 16-bit register that controls the speed and resolution of the on-chip ADCs. Note: If ADCFLT is modified, the current and voltage/temperature ...
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ADuC7039 Table 32. ADC Conversion Rates and Settling Times Chop Enabled Averaging Factor Yes No Yes Yes N additional time of approximately 60 μs per ADC is required before the first ADC result ...
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ADC Configuration Register Name: ADCCFG Address: 0xFFFF051C Default Value: 0x00 Access: Read/write Function: The 8-bit ADC configuration MMR controls extended functionality related to the on-chip ADCs. Table 34. ADCCFG MMR Bit Designations Bit Description 7 Analog ground switch enable. This ...
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ADuC7039 Current Channel ADC Offset Calibration Register Name: ADC0OF Address: 0xFFFF0530 Default Value: Part specific, factory programmed Access: Read/write Function: This ADC offset MMR holds a 16-bit offset calibration coefficient for the I-ADC. The register is configured at power-on with ...
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Current Channel ADC Result Counter Limit Register Name: ADC0RCL Address: 0xFFFF0548 Default Value: 0x0001 Access: Read/write Function: This 16-bit MMR sets the number of conver- sions required before an ADC interrupt is generated. By default, this register is set to ...
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ADuC7039 ADC SINC3 DIGITAL FILTER RESPONSE The overall frequency response on all ADuC7039 ADCs is dominated by the low-pass filter response of the on-chip sinc3 digital filters. The sinc3 filters are used to decimate the ADC Σ-Δ modulator output data ...
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In ADC low power mode, the ADC, Σ-Δ modulator clock is no longer driven at 512 kHz but is driven directly from the on-chip low power (128 kHz) oscillator. Subsequently, for the same ADCFLT configurations in normal mode, all filter ...
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ADuC7039 ADC Calibration As shown in detail in the top level diagrams (Figure 11 and Figure 12), the signal flow through all ADC channels can be described in the following steps input voltage is applied through an input ...
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Understanding the Offset and Gain Calibration Registers The output of the average block in the ADC signal flow can be considered a fractional number with a span for a ±full-scale input of approximately ±0.75. The span is less than ±1.0 ...
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ADuC7039 The fast temperature option cannot be used on the first con- version after ADC power-on. It can only be set after at least the first ADC interrupt. Waiting for a valid ADC result is not necessary. Also, a restriction ...
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POWER SUPPLY SUPPORT CIRCUITS The ADuC7039 integrates two on-chip, low dropout (LDO) regulators that are driven directly from the battery voltage to generate a 2.6 V internal supply. This 2.6 V supply is then used as the supply voltage for ...
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ADuC7039 SYSTEM CLOCKS The ADuC7039 integrates a flexible clocking system that can be clocked from one of two integrated on-chip oscillators: a precision oscillator or a low power oscillator. Each of the internal oscillators is divided by four to generate ...
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The operating mode and clocking mode are controlled using two MMRs, PLLCON and POWCON, and the status of the PLL, PLL lock and PLL interrupt, is indicated by PLLSTA recommended that before powering down the ADuC7039, switch the ...
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ADuC7039 PLLSTA Register Name: PLLSTA Address: 0xFFFF0400 Default Value: 0xXX Access: Read only Function: This 8-bit register allows user code to monitor the lock state of the PLL. Table 37. PLLSTA MMR Bit Designations Bit Description Reserved. ...
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Table 38. PLLCON MMR Bit Designations Bit Description Reserved. These bits should be written user code PLL clock source lower power oscillator precision oscillator the user ...
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ADuC7039 Table 39. POWCON MMR Bit Designations Bit Description Reserved. These bits should be written Precision oscillator enable. This bit is set by the user to enable the precision oscillator. This bit is cleared ...
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OSCILLATORS CALIBRATION The ADuC7039 features two oscillators and two calibration schemes: • The low power oscillator can be calibrated from the precision oscillator or from the LIN communication. The trim value can also be modified by user code. • The ...
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ADuC7039 OSCCON Register Name: OSCCON Address: 0xFFFF0440 Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the low power oscillator calibration routine. Table 40. OSCCON MMR Bit Designations Bit Description Reserved. Should be written as 0. ...
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OSCVAL0 Register Name: OSCVAL0 Address: 0xFFFF0448 Default Value: 0x00 Access: Read only Function: This 9-bit counter is clocked from the 128 kHz precision oscillator. OSCVAL1 Register Name: OSCVAL1 Address: 0xFFFF044C Default Value: 0x0000 Access: Read only Function: This 10-bit counter ...
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ADuC7039 LOCMAX Register Name: LOCMAX Address: 0xFFFF048C Default Value: 0x00000 Access: Read/write Function: Maximum limit expectable in the LINBR for a predefined baud rate. LOCMIN Register Name: LOCMIN Address: 0xFFFF0490 Default Value: 0x00000 Access: Read/write Function: Minimum limit expectable in ...
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Table 43. LOCSTA MMR Bit Designations Bit Description Reserved. Read 0. 2 Low power oscillator trim value modified. This bit is set by hardware when the precision oscillator trim value is altered. This bit is cleared by ...
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ADuC7039 INTERRUPT SYSTEM There are 10 interrupt sources on the ADuC7039 that are con- trolled by the interrupt controller. Most interrupts are generated from the on-chip peripherals such as the ADC and timers. The ARM7TDMI-S CPU core only recognizes interrupts ...
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IRQ The IRQ is the exception signal to enter the IRQ mode of the processor used to service the general-purpose interrupt handling of internal and external events. All 32 bits are logically OR’ create a ...
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ADuC7039 TIMERS The ADuC7039 features three general-purpose timers/counters: • Timer0, or general-purpose timer • Timer1, or wake-up timer • Timer2, or watchdog timer Timers are started by writing data to the control register of the corresponding timer (TxCON). The counting ...
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UNSYNCHRONIZED SIGNAL CORE CLOCK (FCORE) DOMAIN As can be seen from Figure 23, the MMR logic and core timer logic reside in separate and asynchronous clock domains. Any data coming from the MMR core-clock domain and being passed to the ...
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ADuC7039 TIMER0—GENERAL-PURPOSE TIMER Timer0 is a general-purpose 16-bit count-up/count-down timer. Timer0 is clocked from the core clock with a prescalar of either 1 or 16,384. This gives a minimum resolution of 1.6 ms with a prescalar of 16,384, and the ...
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CORE CLOCK FREQUENCY Table 46. T0CON MMR Bit Designations Bit Description Reserved. 5 Timer0 mode. This bit is set by user code to operate in periodic mode. This bit is cleared by user code to operate in ...
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ADuC7039 TIMER1—WAKE-UP TIMER Timer1 is a 32-bit wake-up timer (count-down or count-up) with a programmable prescalar. The selected clock source, core clock, or low power oscillator can be scaled by a factor of 1, 16, 256, or 32,768. The wake-up ...
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LOW POWER OSCILLATOR CORE CLOCK FREQUENCY Table 47. T1CON MMR Bit Designations Bit Description Reserved. These bits should be written Timer1 mode. This bit is set by user code to operate in periodic mode. ...
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ADuC7039 TIMER2—WATCHDOG TIMER Timer2 has two modes of operation: normal mode and watchdog mode. The watchdog timer is used to recover from an illegal software state. Once enabled, it requires periodic servicing to prevent it from forcing a reset of ...
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LOW POWER OSCILLATOR Table 48. T2CON MMR Bit Designations Bit Description Reserved. These bits are reserved and should be written user code. 8 Count up/count down enable. This bit is set by user code ...
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ADuC7039 GENERAL-PURPOSE INPUT/OUTPUT The ADuC7039 features six general-purpose bidirectional input/output (GPIO) pins. In general, the GPIO pins have multiple functions that can be configured by user code. By default, the GPIO pins are configured in GPIO mode. All GPIO pins ...
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GPIO Port Control Register Name: GPCON Address: 0xFFFF0D00 Default Value: 0x00000000 Access: Read/write Function: The 32-bit MMR selects the pin function for each port pin. Table 50. GPCON MMR Bit Designations Bit Description Reserved. These bits are ...
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ADuC7039 GPIO Port Data Register Name: GPDAT Address: 0xFFFF0D10 Default Value: 0x000000FF Access: Read/write Function: This 32-bit MMR configures the direction of the GPIO pins. This register also sets the output value for GPIO pins configured as outputs and reads ...
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GPIO Port Set Register Name: GPSET Address: 0xFFFF0D14 Default Value: N/A Access: Write only Function: This 32-bit MMR allows user code to individually bit address external GPIO pins to set them high only. User code can accomplish this using the ...
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ADuC7039 GPIO Port Clear Register Name: GPCLR Address: 0xFFFF0D18 Default Value: N/A Access: Write only Function: This 32-bit MMR allows user code to individually bit address external GPIO pins to clear them low only. User code can accomplish this using ...
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SERIAL PERIPHERAL INTERFACE (SPI) The ADuC7039 integrates a complete hardware serial peri- pheral interface (SPI) on-chip. SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full ...
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ADuC7039 SPI Status Register Name: SPISTA Address: 0xFFFF0A00 Default Value: 0x0000 Access: Read only Function: This 16-bit MMR contains the status of the SPI interface in both master and slave modes. Table 54. SPISTA MMR Bit Designations Bit Description 15 ...
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SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the SPI peripheral in both master and slave modes. Table 55. SPICON MMR Bit Designations Bit Description SPI IRQ mode ...
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ADuC7039 Bit Description 4 SPI wired or mode enable bit. This bit is set enable open-drain data output enable. External pull-ups are required on data out pins. Clear this bit for normal output levels. 3 Serial clock ...
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HIGH VOLTAGE PERIPHERAL CONTROL INTERFACE The ADuC7039 integrates a number of high voltage circuit functions that are controlled and monitored through a regis- tered interface consisting of two MMRs, namely, HVCON and HVDAT. The HVCON register acts as a command ...
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ADuC7039 High Voltage Interface Control Register Name: HVCON Address: 0xFFFF0804 Default Value: Updated by kernel Access: Read/write Function: This 8-bit register acts as a command byte interpreter for the high voltage control interface. Bytes written to this register are interpreted ...
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High Voltage Configuration Register Name: HVCFG Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read/write Function: This 8-bit register controls the function of high voltage circuits on the ADuC7039. This register is not an MMR ...
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ADuC7039 High Voltage Status Register Name: HVSTA Address: Indirectly addressed via the HVCON high voltage interface Default Value: 0x00 Access: Read only, this register should only be read on a high voltage interrupt Function: This 8-bit, read-only register reflects a ...
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HV Configuration Following is a code example to enable LIN. char HVstatus; do{ HVDAT = 0x01; HVCON = 0x08; do{ HVstatus = HVCON; } while(HVstatus & 0x1); } while (!(HVstatus & 0x4)); It is best practice to implement the high ...
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ADuC7039 LIN (LOCAL INTERCONNECT NETWORK) INTERFACE LIN PHYSICAL INTERFACE The ADuC7039 features a high voltage physical interface between the ARM7 MCU core and an external LIN bus. The LIN interface operates as a slave only interface, operating from 1 kB ...
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LIN DIAGNOSTIC The ADuC7039 features a short-circuit protection on the LIN pin short-circuit condition is detected on the LIN pin, HVSTA[0] is set. This generates a high voltage interrupt if enabled in IRQEN[10]. This bit is cleared by ...
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ADuC7039 LINCON Register Name: LINCON Address: 0xFFFF0700 Default Value: 0x0000 Access: Read/write Function: This 16-bit MMR controls the LIN peripheral. LINCS Register Name: LINCS Address: 0xFFFF0704 Default Value: 0xFF Access: Read/write Function: 8-bit checksum register. LINBR Register Name: LINBR Address: ...
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Table 61. LINCON MMR Bit Designations Bits Description Reserved. 12 LIN bypass bit. This bit is set user code to take control of the LIN transceiver alone, for LIN conformance test. This bit is ...
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ADuC7039 Table 62. LINSTA MMR Bit Designations Bits Description Reserved. 10 LIN wake-up interrupt. This bit is set if LIN woke up the ADuC7039. The wake-up functionality (LINWU MMR) is only used when POWCON[ This ...
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PART IDENTIFICATION For traceability, part identification is available at power-up. Information such as manufacturing lot ID, silicon mask revision, and kernel revision are available in the internal ARM register at power-up (R4 to R6), as described in Table 64 and ...
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ADuC7039 System Identification FEEADR Name: FEEADR Address: 0xFFFF0E10 Default Value: 0xF009 Access: Read/write Function: This 16-bit register dictates the address upon which any Flash/EE command executed via FEECON acts. Note: This MMR is also used to identify ADuC703x family member ...
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RECOMMENDED SCHEMATIC This schematic contains external components that are recommended for proper operation of the ADuC7039. VBAT 0.1µF 10Ω 10µF IIN+ SHUNT REG_AVDD JTAG ADAPTOR VBAT TDO TCK TMS TDI 27 VDD 0.1µF 12 IIN+ ...
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... ADuC7039 OUTLINE DIMENSIONS PIN 1 INDICATOR 1.00 0.95 0.90 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range ADuC7039BCP6Z −40°C to 115°C ADuC7039BCP6Z-RL −40°C to 115°C EVAL-ADUC7039QSPZ RoHS Compliant Part. 6.10 0.30 6.00 SQ 0.25 5.90 0. 0.50 BSC 17 16 0.65 TOP VIEW BOTTOM VIEW ...
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NOTES Rev Page ADuC7039 ...
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ADuC7039 NOTES ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08463-0-8/10(B) Rev Page ...