EZ80F910100KIT Zilog, EZ80F910100KIT Datasheet - Page 33

• Manufacturer Part Number: EZ80F910100KIT
• Description: KIT DEV FOR EZ80F91 W/C-COMPILER
• Manufacturer: Zilog
• Series: eZ80 Acclaim!®r
• Type: MCUr

Specifications of EZ80F910100KIT

• Contents: Dev. Board, Ethernet Module, Cable, Power Supply and Software
• For Use With/related Products: eZ80F91
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 269-3388

UM017001-0404
eZ80F91 Data Bus
Flash Data Bus
CPU Clock
CS0
CS1
WR
RD
Figure 7. Possible Bus Contention without Fast Buffer
Essentially, after the eZ80F91 device accesses Flash memory, a time
duration of 8.8 ns + 25 ns = 33.8 ns can transpire before Flash memory
stops driving the data bus. At that time, the eZ80F91 device is well into
the next bus cycle. Assuming this next cycle is the Memory Write cycle,
then the data output of the eZ80F91 device is valid not later than
T3 = 7.5 ns, and the write pulse is asserted not later than 4.5 ns after the
falling edge of the CPU Clock (14.5 ns from the rising edge if the CPU
Clock is 50 MHz). The duration of bus contention, T
the eZ80F91 Product Specification (PS0192) for assistance.
7.5 ns = 26.3 ns. Refer to the External Memory Write Timing diagram in
T6
PRELIMINARY
eZ80F91 Modular Development Kit
Data In
T3
Bus Contention
eZ80F91 Mini Enet Module
T4
Data Out
T
OD
CON,
User Manual
is 33.8 ns –
23