Z84C9000ZCO Zilog, Z84C9000ZCO Datasheet - Page 10

• Manufacturer Part Number: Z84C9000ZCO
• Description: KIO + Z84C01 DEVELOPMENT BOARD
• Manufacturer: Zilog
• Type: MPUr

Specifications of Z84C9000ZCO

• Contents: Circuit Board, Software and Documentation
• For Use With/related Products: Z84C90
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Pin Descriptions
PS011802-0902
PC0 (WT/RDYB)
CLK/TRG3
RESET
Figure 3. 100-Pin LQFP Configuration
A0–A3. Address bus (inputs). Used to select the port/register for each bus cycle.
ARDY, BRDY. Port Ready (outputs, Active High). These signals indicate that the port is
ready for a data transfer. In Mode 0, the signal indicates that the port has data available to
the peripheral device. In Mode 1, the signal indicates that the port is ready to accept data
from the peripheral device. In Mode 2, ARDY indicates that Port A has data available for
the peripheral device, but that the data is not be placed onto PA0–PA7 until the ASTB sig-
nal is Active. BRDY indicates that Port A is able to accept data from a peripheral device.
DCDA
DCDB
CSTA
CTSB
RxCB
RxDB
TxDB
TxCB
IORQ
GND
V
NC
NC
CS
M1
RD
NC
NC
A0
A1
A2
A3
CC
76
80
85
90
95
100
75
1
5
70
100-Pin LQFP
10
65
15
60
20
KIO Serial/Parallel Counter Timer
55
51
25
50
45
40
35
30
26
NC
NC
GND
GND
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
BRDY
BSTB
ARDY
ASTB
ZC/TO3
ZC/TO2
ZC/TO1
ZC/TO0
IE1
IE0
V
NC
NC
CC
Z84C90
5