Z84C9000ZCO Zilog, Z84C9000ZCO Datasheet - Page 30
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Z84C9000ZCO
Manufacturer Part Number
Z84C9000ZCO
Description
KIO + Z84C01 DEVELOPMENT BOARD
Manufacturer
Zilog
Type
MPUr
Datasheet
1.Z84C9010VEG.pdf
(31 pages)
Specifications of Z84C9000ZCO
Contents
Circuit Board, Software and Documentation
For Use With/related Products
Z84C90
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Precautions & Limitations
PS011802-0902
The following describe the limitations of Revision A of the Z84C90 KIO.
Problem:
Daisy-chain. If the KIO has an Interrupt Pending during and Interrupt Acknowledge
cycle, KIO misses the status of the IE1 pin. This produces vector contention if there is a
higher interrupting device. It works fine if only one device is in the system.
Work Around:
There is no problem if the application has only one peripheral in the daisy chain. For two
or more peripherals in the system, a “hardware workaround circuit” is needed. Please con-
tact your local Zilog representatives to get more detailed information.
Problem:
Reset. KIO requires the M1 signal to exit from Reset state. If the M1 signal is not
received, the KIO can not be programmed. This is not a problem for users of the Z80
CPU.
Workaround:
If the CPU is other than a Z80, an M1 signal is needed to exit RESET status. Otherwise,
the KIO can not be programmed.
Problem:
Port C. When Port C is used as Parallel I/O (not as SIO’s modem signals) and there is a
status change on PC1 or PC6, the status of SYNCA or SYNCB (SIO cell) also changes.
Work Around:
Before using Port C as a parallel port, set the SIO modem signal mode back to Port C. This
procedure avoids the problem.
Problem:
Interrupt Acknowledge cycle. The KIO modifies the contents of the KIO control register
(specifically, the KIO modifies the daisy-chain configuration) if the CE pin is active dur-
ing the Interrupt Acknowledge cycle (with other conditions satisfied).
KIO Serial/Parallel Counter Timer
Z84C90
25