ST7MDT2-EPB2/US STMicroelectronics, ST7MDT2-EPB2/US Datasheet - Page 21
ST7MDT2-EPB2/US
Manufacturer Part Number
ST7MDT2-EPB2/US
Description
BOARD PROGRAMMING SGL POS ST7
Manufacturer
STMicroelectronics
Type
MCUr
Specifications of ST7MDT2-EPB2/US
Contents
Programmer Board
For Use With/related Products
ST72311, ST72124, ST72314, ST72334
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- Current page: 21 of 153
- Download datasheet (3Mb)
DATA EEPROM (Cont’d)
6.6 REGISTER DESCRIPTION
CONTROL/STATUS REGISTER (CSR)
Read /Write
Reset Value: 0000 0000 (00h)
Bit 7:3 = Reserved, forced by hardware to 0.
Bit 2 = IE Interrupt enable
This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when the software enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled
7
0
0
0
0
0
IE
LAT
PGM
0
Bit 1 = LAT Latch Access Transfer
This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode
Bit 0 = PGM Programming control and status
This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware and an interrupt is generated
if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress
Note: if the PGM bit is cleared during the program-
ming cycle, the memory data is not guaranteed
ST72334J/N, ST72314J/N, ST72124J
21/153
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